100
µPD750008 USER'S MANUAL
When bit 3 is set to 1, the BT is cleared, and the basic interval ltimer/watchdog timer interrupt request flag(IRQBT) is also cleared (to start the basic interval timer/watchdog timer).A RESET signal clears the interval timer to 0, and the longest interrupt request signal generation intervaltime is set.Figure 5-24. Format of the Basic Interval Timer Mode Register
Address
F85H
3210
BTM3 BTM2 BTM1 BTM0
Symbol
BTM
Input clock specification
00
10
11
0
1
0
111
When 1 is written to this bit, the basic interval timer/watchdog timer operation starts
(the counter and the interrupt request flag are cleared).
When the operation starts, this bit is automatically reset to 0.
Basic interval timer/watchdog timer start control bit
Interrupt interval time
(wait time for releasing standby)
f
X
/2
12
(1.02 kHz)
f
X
/2
9
(8.18 kHz)
f
X
/2
7
(32.768 kHz)
f
X
/2
5
(131 kHz)
2
20
/f
X
(250 ms)
2
17
/f
X
(31.3 ms)
2
15
/f
X
(7.82 ms)
2
13
/f
X
(1.95 ms)
Not to be set —
Input clock specification
00
10
11
0
1
0
111
Interrupt interval time
(wait time for releasing standby)
f
X
/2
12
(1.46 kHz)
f
X
/2
9
(11.7 kHz)
f
X
/2
7
(46.9 kHz)
f
X
/2
5
(188 kHz)
2
20
/f
X
(175 ms)
2
17
/f
X
(21.8 ms)
2
15
/f
X
(5.46 ms)
2
13
/f
X
(1.37 ms)
Not to be set —
(f
X
= 6.00 MHz)
(f
X
= 4.19 MHz)
Other than
above
Other than
above