146
µPD750008 USER'S MANUAL
Serial interface operation mode selection bit (W)
CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin function
0 1 1 SIO7-0 <—> XA SB0/P02 (N-ch P03 input
(Transfer starting with MSB) open-drain I/O)
1P02 input SB1/P03 (N-ch
open-drain I/O)
Serial clock selection bit (W)
CSIM1 CSIM0 Serial clock SCK pin mode
0 0 External clock applied to SCK pin Input
0 1 Timer/event counter output (TOUT0) Output
10f
X
/26 (65.5 kHz)
11
Remark The value at 4.19 MHz is indicated in parentheses.
(b) Serial bus interface control register (SBIC)
To use the two-wire serial I/O mode, set SBIC as shown below. (For details on SBIC format, see (2)
in Section 5.6.3.)
SBIC is manipulated using a bit manipulation instruction.
When the RESET signal is input, SBIC is set to 00H.
In the figure below, the hatched portions indicate the bits used in the two-wire serial I/O mode.
Remark (W): Write only
Command trigger bit (W)
CMDT Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO latch is
cleared. Then the CMDT bit is automatically cleared.
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
FE2H SBIC
76543210
Address
Bus release trigger bit (W)
Command trigger bit (W)
Do not use these bits in the
two-wire serial I/O mode.