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ยตPD750008 USER'S MANUAL
(3) Configurations of the INT0, INT1, and INT4 circuits
(a) As shown in Figure 6-4 (a), the INT0 circuit accepts an external interrupt at its rising or falling edge.
The edge to be detected can be selected.
The INT0 circuit has a noise elimination function (see Figure 6-5), called a noise eliminator, using
a sampling clock, which removes pulses shorter than two sampling clock cyclesNote as noise. The
INT0 circuit may accept pulses which are longer than one sampling clock cycle and shorter than two
cycles as interrupts depending on the sampling timing (see Figure 6-4 (a)). The circuit is sure to accept
pulses equal to or longer than two sampling clock cycles as interrupts.
The INT0 pin is supplied with sampling clock F or fX/64, whichever is selected by bit 3 (IM03) of the
INT0 edge detection mode register (IM0).
Bit 0 (IM00) and bit 1 (IM01) of the INT0 edge detection mode register (IM0) are used to select a
detection edge.
Figure 6-6 (a) shows the format of IM0. A 4-bit memory manipulation instruction is used to set IM0.
A RESET signal clears all bits to 0, and a rising edge is specified to be detected.
Note When the frequency of a sampling clock is F, these cycles are equal to 2tCY. When the
frequency of a sampling clock is fX/64, these cycles are equal to 128/fX.
Cautions 1. Input a pulse wider than two sampling clock cycles to the INT0/P10 pin. Otherwise,
the pulse is suppressed as noise by a noise eliminator when the pin is used as
a port.
2. When the noise eliminator is selected (IM02 is set to 0), INT0 does not operate
in standby mode because INT0 requires a clock for sampling. Do not select the
noise eliminator when using INT0 to release standby mode (set IM02 to 1).
(b) As shown in Figure 6-4 (b), the INT1 circuit accepts an external interrupt at its rising or falling edge.
The INT1 edge detection mode register (IM1) is used to select a detection edge.
Figure 6-6 (b) shows the format of IM1. A bit manipulation instruction is used to set IM1. A RESET
signal clears all bits to 0, and a rising edge is specified to be detected.
(c) As shown in Figure 6-4 (c), the INT4 circuit accepts an external interrupt at its rising and falling edges.