Main
PD750008
USER'S MANUAL
Page
Page
Major Changes
The mark * shows major revised points.
Page
Page
Page
Page
CONTENTS
Page
Page
Page
Page
LIST OF FIGURES (1/4)
LIST OF FIGURES (2/4)
LIST OF FIGURES (3/4)
LIST OF FIGURES (4/4)
LIST OF TABLES (1/2)
Page
Page
CHAPTER 1 GENERAL
2
1.1 FUNCTION OVERVIEW
Page
Page
5
CHAPTER 1 GENERAL 1.4 BLOCK DIAGRAM
( )
6
Note Connect IC (VPP) to VDD, keeping the wiring as short as possible. Remark ( ) : PD75P0016.
7
Note Connect IC (VPP) to VDD, keeping the wiring as short as possible. Remark ( ) : PD75P0016.
Page
CHAPTER 2 PIN FUNCTIONS
Page
11
CHAPTER 2 PIN FUNCTIONS Table 2-2. Non-Port Pin Functions
Page
Page
Page
Page
Page
Page
Page
19
CHAPTER 2 PIN FUNCTIONS
P-ch
Note
IN/OUT
20
2.4 CONNECTION OF UNUSED PINS Table 2-3. Connection of Unused Pins
Note ( ): PD75P0016
CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP
Page
Page
24
Figure 3-2. Data Memory Organization and Addressing Range of Each Addressing Mode
Remark : Don't care
25
Table 3-1. Addressing Modes
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
37
Figure 3-5. General Register Configuration (4-bit Processing)
38
Figure 3-6. General Register Configuration (8-bit Processing)
Page
40
Figure 3-7. PD750008 I/O Map (1/5)
41
Figure 3-7. PD750008 I/O Map (2/5)
42
Figure 3-7. PD750008 I/O Map (3/5)
43
Figure 3-7. PD750008 I/O Map (4/5)
Note Whether a bit can be read or written depends on the bit.
44
Figure 3-7. PD750008 I/O Map (5/5)
CHAPTER 4 INTERNAL CPU FUNCTIONS
Page
Page
Page
49
Figure 4-3. Program Memory Map (in PD750004)
50
Figure 4-4. Program Memory Map (in PD750006)
51
Figure 4-5. Program Memory Map (in PD750008)
52
Figure 4-6. Program Memory Map (in PD75P0016)
Page
Page
Page
Page
Page
Page
59
Figure 4-11. Format of Stack Pointer and Stack Bank Select Register
Note PC12 and PC13 are 0 in the PD750004. PC13 is 0 in the PD750006 and PD750008.
60
Figure 4-13. Data Restored from the Stack Memory (Mk I Mode)
61
Figure 4-15. Data Restored from the Stack Memory (Mk II Mode)
Page
Page
Page
Page
Page
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Page
69
Figure 5-2. Configurations of Ports 0 and 1
70
Figure 5-3. Configurations of Ports 2 and 7
Note For port 7 only
71
Figure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3)
Internal bus
Note For port 6n only
72
Figure 5-5. Configurations of Ports 4 and 5
73
Figure 5-6. Configuration of Port 8
Page
75
Figure 5-7. Formats of Port Mode Registers
Port mode register group A
Port mode register group B
Port mode register group C
Page
Page
78
Table 5-2. I/O Pin Manipulation Instructions
Page
80
Table 5-3. Operations by I/O Port Manipulation Instructions
<1> : Represents an addressing mode PORTn.bit or PORTn.@L.
Page
Page
Page
84
Page
Page
87
Figure 5-12. Format of the Processor Clock Control Register
Remarks 1. f
: Output frequency from the main system clock oscillator 2. f
: Output frequency from the subsystem clock oscillator
Page
Page
Page
Page
Page
Page
Page
Page
Page
97
Note
Caution Be sure to write a 0 in bit 2 of the CLOM.
is the CPU clock selected by PCC.
Page
Page
100
Page
Page
Page
Page
Page
106
107
Remark ( ) for fW = 32.768 kHz
Page
109
TOUT0
Figure 5-28. Block Diagram of the Timer/Event Counter (Channel 0)
110
Figure 5-29. Block Diagram of the Timer Counter (Channel 1)
Page
112
Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format
= 4.19 MHz
Count pulse (CP) selection bit
= 6.00 MHz
113
Figure 5-31. Timer Counter Mode Register (Channel 1) Format
= 4.19 MHz
Count pulse (CP) select bit
= 6.00 MHz
Page
115
Count pulse (CP) selection bit
116
Page
Page
Page
Page
Page
Page
Page
Page
125
Figure 5-39. Block Diagram of the Serial Interface
Page
Page
Page
129
Remark x: Dont care Serial clock selection bit (W)
Remarks 1. Each mode can be selected using CSIE, CSIM3, and CSIM2.
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
161
Figure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master)
Figure 5-61. Operations of RELT, CMDT, RELD, and CMDD (Slave)
Page
Page
Page
165
Table 5-10. Various Signals Used in the SBI Mode (1/2)
166
Table 5-10. Various Signals Used in the SBI Mode (2/2)
Notes 1. When WUP = 0, IRQCSI is always set on the ninth rising edge of the SCK signal.
Page
Page
169
Figure 5-67. Address Transfer Operation from Master Device to Slave Device (WUP = 1)
170
Figure 5-68. Command Transfer Operation from Master Device to Slave Device
171
Figure 5-69. Data Transfer Operation from Master Device to Slave Device
172
Figure 5-70. Data Transfer Operation from Slave Device to Master Device
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
CHAPTER 6 INTERRUPT AND TEST FUNCTIONS
184
Figure 6-1. Block Diagram of Interrupt Control Circuit*
Note Noise eliminator (when the noise eliminator is selected, standby mode cannot be released.)
185
<
<
Page
Page
189
Figure 6-3. Interrupt Priority Specification Register
Page
191
INT4
(c) Configuration of the INT4 circuit
(b) Configuration of the INT1 circuit
INT4/P00
192
Figure 6-5. I/O Timing of a Noise Eliminator
Remark tSMP = tCY or 64/fX
193
Figure 6-6. Format of Edge Detection Mode Registers (a) INT0 edge detection mode register (IM0)
(b) INT1 edge detection mode register (IM1)
Page
195
Page
Page
Page
Page
Page
Page
Page
203
(1) Interrupt enable/disable
Interrupt disabled
INT0 and INTT0 enabled INTT0 enabled Interrupt disabled
<Main program> <1> Reset <2> EI IE0 EI IET0 <3> EI <4> DI IE0 <5> DI
204
; RBE = 0
<INT0 service program>
<5> RETI
Status 1
Page
206
(4) Execution of held interrupts (interrupt requests when interrupts are disabled)
RETI
<2> EI
RETI
207
(5) Execution of held interrupts two interrupts with lower priority occur concurrently
<INTT0 service routine>
RETI
<1>
Page
209
<1> INTCSI
<5>
<3> INTT0
Status 1
Page
Page
212
Figure 6-10. Block Diagram of the INT2 and KR0 to KR7 Circuits
Page
Page
CHAPTER 7 STANDBY FUNCTION
Page
Page
Page
Page
Page
=
..
Page
Page
Page
CHAPTER 8 RESET FUNCTION
226
Table 8-1. Status of the Hardware after a Reset (1/2)
227
CHAPTER 8 RESET FUNCTION Table 8-1. Statuses of the Hardware after a Reset (2/2)
Page
CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)
Page
231
Page
Page
Page
CHAPTER 10 MASK OPTION
Page
CHAPTER 11 INSTRUCTION SET
Page
Page
Page
Page
Page
243
(3) Explanation of symbols used for the addressing area column
Page
Page
246
Page
Page
249
Note The shaded portion is supported in Mk II mode only.
250
251
Page
Page
Page
255
256
257
258
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
APPENDIX A FUNCTIONS OF THE PD75008, PD750008, AND PD75P0016
A
Page
301
APPENDIX B DEVELOPMENT TOOLS
*
302
PROM programming tools
303
APPENDIX B DEVELOPMENT TOOLS
Page
305
APPENDIX B DEVELOPMENT TOOLS
+
Development Tool Configuration
Page
Page
Page
APPENDIX C MASKED ROM ORDERING PROCEDURE
C
Page
APPENDIX D INSTRUCTION INDEX
D
Page
Page
Page
Page
Page
APPENDIX E HARDWARE INDEX
E
Page
Page
Page
321
APPENDIX F REVISION HISTORY
Major revisions in this edition are shown below. The revised chapters refer to this edition.
F
