150-409-115-05, Issue 5

Technical Specifications

 

 

TECHNICAL SPECIFICATIONS

HDSL

Line Code

1040 kbps, 2B1Q full duplex

Output

+13 dBm

Line Impedance

135 Ω

Resistive Signature

Input/Output: 25 Ω (maximum)

 

Line Output DC: 25 Ω (maximum)

Start-up Time (per span)

15 seconds (typical), 30 seconds

 

(maximum)

Line Clock Rate

 

Internal Stratum 4 clock

 

Power Consumption

 

3.0 W (nominal), 3.2 W (maximum)

Maximum Provisioning Loss

35 dB @ 260 kHz, 135 Ω

Wander and Jitter

Nominal - The absence of an HDSL framer from the EDU-409 List 1 reduces the Doubler Unit’s effect on a circuit’s overall wander and jitter to second order insignificance when compared to the wander and jitter of other circuit modules.

Latency

80 microseconds (maximum either direction)

Mounting

Single 239 T1 Mechanics slot

Electrical Protection

Secondary surge and power cross protection on all HDSL ports

EDU-409 List 1

January 26, 2000

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