Advantech AIMB-250 user manual Ecc

User’s Manual

•Integrated LAN controller

•System Management Bus (SMBus) compatible with most IC devices; ICH4 has both bus master and slave capability

•AC ’97 2.3 compliant link for audio and telephony codecs; up to 6 channels

•Low Pin Count (LPC) interface

•FWH Interface (FWH Flash BIOS support)

•Alert on LAN* (AOL and AOL2)

1.6.3Intel 855GME and ICH4

The Intel 855GME GMCH component provides the processor interface, DDR SDRAM interface, display interface, and Hub Interface in an Intel 855GME chipset platform. The Intel 855GME GMCH is optimized for the Mobile Intel Pentium 4 Processor-M, Mobile Intel Celeron processor and Intel Celeron M processor. It supports a single channel of DDR SDRAM memory. Intel 855GME Chipset contains advanced power management logic. The Intel 855GME Chipset platform supports the fourth generation mobile I/O Controller Hub to provide the features required by a mobile platform.

The Intel 855GME GMCH is in a 732-pin Micro-FCBGA package and contains the following functionality:

•Supports single Intel processor configurations at 400-MHz or 3 GB/s

•1.2-1.30-V AGTL+ host bus supporting 32-bit host bus addressing with Enhanced Intel SpeedStep® technology (Intel Celeron M processor and Intel Celeron Processor do not support Enhanced Intel SpeedStep Technology).

•System Memory supports 200/266-MHz (SSTL_2) DDR DRAM Up to 1 GB (with 256-Mb technology and two SO-DIMMs) of PC1600/2100 DDR SDRAM without

ECC

•Integrated graphics capabilities, including 3D rendering acceleration and 2D hardware acceleration

•Integrated 350-MHz, 24-bit RAMDAC with pixel resolution up to 1600x1200 at 85-Hz and up to 1920x1440 @ 60 Hz

•One Dedicated Dual Channel LFP LVDS interface with frequency range of 25 MHz to 112 MHz (single channel/dual channel) for support up to SXGA+ (1400x1050 @ 60 Hz) panel resolutions with maximum pixel depth of 18-bpp

•Integrated PWM (Pulse Width Modulation) interface for LFP backlight inverter control for panel brightness

•One 165-MHz, 12-bit, DVO interface for TV-out encoder and DVI (LVDS transmitter and TMDS transmitter) support I2C and DDC channels supported

•Dual Pipe Independent Display with Tri-view support through LFP, DVO, and CRT

•Deeper Sleep state support

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