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Agilent Technologies FS2334 Header 14 ECC bits only this header is not in any config file

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Header 14 – ECC bits only this header is not in any config file

Logic Analyzer

channel

number

SAMTEC Pin

number SAMTEC Pin

number

Logic Analyzer

channel

number

Signal

name/Logical

Signal Name

Ground 1 2 Ground

Ground 3 4 NC

NC 5 6 NC

Ground 7 8 D0 CB1

20K ohm to

Ground 9 10 Ground

Ground 11 12 D1 DQS8n

20K ohm to

Ground 13 14 Ground

Ground 15 16 D2 DQS8

20K ohm to

Ground 17 18 Ground

Ground 19 20 D3 CB6

20K ohm to

Ground 21 22 Ground

Ground 23 24 D4 CB2

20K ohm to

Ground 25 26 Ground

Ground 27 28 D5 CB7

20K ohm to

Ground 29 30 Ground

Ground 31 32 D6 CB3

20K ohm to

Ground 33 34 Ground

Ground 35 36 D7 Ground

20K ohm to

Ground 37 38 Ground

Ground 39 40 D8 No connection

20K ohm to

Ground 41 42 Ground

Ground 43 44 D9 No connection

20K ohm to

Ground 45 46 Ground

Ground 47 48 D10 No connection

20K ohm to

Ground 49 50 Ground

Ground 51 52 D11 No connection

20K ohm to

Ground 53 54 Ground

Ground 55 56 D12 No connection

Contents

Main FuturePlus Systems Corporation DDR2 DIMM HIGH SPEED PROBE FS2334 Users Manual For use with Agilent Technologies Logic Analy zers Page Page How to reach us Product Warranty Assistance Exclusive Remedies Limitation of warranty Software License Agreement License Agreement Use of the software Sublicensing and Distribution Copies and Adaptations Ownership Introduction Definitions Logic Analyzer Modules Logic Analyzer Machine FS2334 Probe Description Probe Technical Feature Summary Probe Components Signal Assignments on Probe Pods Signal Threshold Voltage Settings Connecting the DDR2 Probe to the Logic Analyzer Test Points Connecting to your Target System Signal Isolation on the Probe Buffered signals on the probe Recommended Logic Analyzer Card Requirements and Configuration files Page Software Requirements Setting up the 169xx Analyzer 169xx Licensing Loading 169xx configuration files and General Purpose Probe Feature Offline Analysis Page TimingZoom Analysis Decoding DDR Commands Taking a Trace, Triggering, and Seeing Measurement Results State Analysis Overview State Analysis Operation Read and Writes above 667MT/s State Analysis Operation Read and Write at 667MT/s or slower State Analysis Operation Read or Write at 800MT/s The process for setting sampling positions at speeds of 800MT/s: State analysis calibration procedure Page Page Adjusting the sampling positions with controlled stimulus Page State Display DDR2 Protocol Checking and Performance Tool (FS1140) FS1140 Installation and Licensing Loading the FS1140 Setting up the FS1140 DDR2 Tool Statistics Errors Export Repetitive Run Timing Analysis Export Page Appendix FS2334 Signal to Logic Analyzer Connector and Channel Mapping Header 1 - Command Page Header 2 - Command Page Header 3 - Write Page Header 4 - Write Page Header 5 - Write Page Header 14 ECC bits only this header is not in any config file Page Header 6 Write Page Header 7 -Write Page Header 8 - Write Page Header 12 Read Duplicates - only data signals Page Header 10 - Read Duplicates - only data signals Page Header 11 Read Duplicates - only data signals Page Header 9 Read Duplicates - only data signals Page Header 13 Read Duplicates - only data signals