UART Tx C | OUT_6 (RS423) |
UART Rx C | IN_6 (RS232) |
UART Tx D | OUT_7 (RS423) |
UART Rx D | IN_7 (RS232) |
Master interrupt enable when ‘1’ gates all interrupts through to the PCI host. When ‘0’ the interrupts can be used for status without interrupting the host.
Force interrupt is used for test and software development purposes to create an interrupt request. 1 = assert interrupt request. 0 = normal operation. Useful to stimulate interrupt acknowledge routines for development.
SCC reset causes a hardware reset of the SCC. In order to accomplish this, set this bit high and then low. All registers and modes in the SCC will revert to the reset state.
UART reset causes a hardware reset of the UART. The process is the same as the SCC.
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