Theory of Operation
The PMC-4U is designed for transferring data from one point to another with a variety of serial protocols.
The PMC-4U features a Xilinx FPGA. The FPGA contains the general control and status registers as well as the interface to the quad UART, SCC, and IO drivers and receivers. Many additional control and status registers reside in the UART and SCC, which are accessed through the Xilinx interface.
The PMC-4U is a part of the PMC Module family of modular I/O products. It meets the PMC and CMC draft Standards. Contact Dynamic Engineering for a copy of this specification. It is assumed that the reader is at least casually familiar with this document and logic design. In standard configuration, the PMC-4U is a Type 1 mechanical with no components on the back of the board and one slot wide, with 10 mm inter-board height.
The PCI interface to the host CPU is controlled by a logic block within the Xilinx. The PMC-4U design requires one wait state for read or write cycles to addresses other than the SCC and UART which require from three for simple read or write operations to nine for the SCC interrupt acknowledge/vector read cycle. The wait states refer to the number of clocks after the PCI core decode before the “terminate with data” state is reached. Two additional clock periods account for the 1 clock delay to decode the signals from the PCI bus and to convert the terminate with data state into the TRDY signal.
The quad UART and dual Serial Communication Controller can handle multiple asynchronous and synchronous protocols and the IO drivers and receivers support a range of electrical interface standards.
Each of the serial interfaces has its own oscillator and on-board baud rate generator to supply a wide range of clock reference frequencies. The SCC can also operate from external clock sources with separate Rx clock input and Tx clock input/output pins for each channel.
Please refer to the XR16C854 and Z85C30 documentation for more information on the operation and capabilities of these devices.
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