I INDEX
A
ADC (analog-to-digital converter) interface, 1-1, 2-2
address bus, 2-3ADSP-21262 processors
clock in signal (DAI_PP2_CLOCKIN), 2-3, 2-4
MIS0 signal, 2-5ADx pins, 1-2
architecture, of this EZ-Extender, 2-1
B
bidirectional drivers, 2-1bill of materials, A-1
block diagram, of this EZ-Extender,2-1board schematic, B-1
breadboard capabilities, -viii, 1-2
C
clock, 2-2
disconnect jumper (P10), 2-5signals, 2-2, 2-3, 2-4
source control switch (SW1), 2-3sources, 2-5
compatible boards, of this EZ-Extender, 1-2connectors
J2 (SPI), 2-5
J3 (SMA), 2-2, 2-5customer support, -x
D
DAI_Px signals, 1-1, 2-3data
bus, 1-2,2-3
transfer (PDAP/HSC), 1-1dimensions, of this EZ-Extender, -viiiDIP switch (SW1), 2-3
direction control switch (SW1), 2-3
E
expansion interface, -vii, 1-2external port, 1-2
F
features, of this EZ-Extender, -viii
G
general-purpose signals, 1-1, 2-2, 2-3
H
HSC (high-speed converter), -viii, 1-1, 2-2
I
interface, ADC and HSC, -viii, 1-1, 2-2
