Configuration Examples for EHWIC 1 
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  | Fragment Frames Received : 0 | |||
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  | Alignment Errors Received : 0  | |||
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  | Symbol Errors Received : 0  | |||
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  | Internal MAC Errors : 0  | |||
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  | =============================================  | 
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  | Bytes Transmitted : 2997  | |||
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  | Frames Transmitted OK : 22  | |||
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  | Broadcast Frames Transmitted OK : 2  | |||
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  | Multicast Frames Transmitted OK : 20  | |||
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  | Underrun Error : 0  | |||
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  | Control Frames Transmitted OK : 4  | |||
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  | 64 byte Frames Transmitted OK : 6  | |||
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  | VLAN Frames Transmitted OK : 0  | |||
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  | PAUSE Frames Transmitted OK : 4  | |||
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  | Oversized Frames Transmitted OK : 0  | |||
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  | Single Collision Frames : 0  | |||
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  | Multiple Collision Frames : 0  | |||
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  | Deferred Frames : 0  | |||
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  | Late Collision Frames : 0  | |||
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  | Frames Aborted due to Excessive Collisions : 0  | |||
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  | Carrier Sense Errors : 0  | |||
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  | ******* HWIC Common Registers at 10000000 *******  | |||
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  | HWIC ID: 0x2  | |||
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  | HWIC Revision: 0x0  | |||
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  | HWIC Status: 0x0  | |||
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  | HWIC DDR TXCRC:0x0  | |||
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  | HWIC Control: 0xC080  | |||
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  | DDR Enable 1 Software Reset 1  | |||
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  | Interrupt Module Reset 0 GDF Module Reset 0  | |||
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  | DMA Module Reset 0 Flow Control Reset 0  | |||
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  | IRQ2 Global Int Mask 1 IRQ1 Global Int Mask 0  | |||
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  | DDR TXCRC Int Mask 0 DDR TXClk Loss Int Mask 0  | |||
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  | TX Fifo Overrun Int Mask 0  | |||
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  | HWIC Interrupt Event: 0x0  | |||
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  | DDR TXCRC Int 0 DDR TXClk Loss Int 0  | |||
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  | TX Fifo Overrun Int 0  | |||
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  | HWIC Diag 1: 0x0  | |||
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  | HWIC Diag 2: 0x1C0F  | |||
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  | ******* HWIC Host Registers at 10FE0000 *******  | |||
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  | Status (0x00):  | |||
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  | Card Present Low 0 Graceful Stop Tx Complete 0  | |||
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  | Config (0x00007322):  | |||
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  | Hwic Reset 0 Hwic Host Reset 0  | |||
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  | Hwic IRQ2 Type Net Hwic IRQ1 Type unknown  | |||
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  | Rx Queue Watermark Enable 0 Auto XOFF When Full 0  | |||
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  | Rx Int On Last 1 Graceful Stop Tx 0  | |||
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  | Generic Rx Enable 0 Generic Tx Enable 0  | |||
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  | DDR Enable 1 Loopback 0  | |||
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  | Error Interrupt Enable (0x34DFF):  | |||
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  | Rx Done Error Int 1 Card Present Change Int 1  | |||
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  | Hwic Int Frame Error Int 0x04 Tx First Last Error Int 1  | |||
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  | Tx Done Error Int 1 IRQ2 Int 0  | |||
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  | IRQ1 Int 1 Host Specific Error Int 1  | |||
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  | Rx Overrun Int 1 DDR RxClk Missing Int 1  | |||
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  | Reg RW Timeout Int 1 Reg RW Error Int 1  | |||
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  | Rx CRC Int 1 Rx Format Error Int 1  | |||
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  | DMA Error Int 1  | |||
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  | Configuring Gigabit Ethernet Enhanced   | 
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