Clevo M860TU manual Sheet 4 Cantiga 1/6, Host

Schematic Diagrams

Cantiga 1/6, Host

					2	H _ D # [ 63 : 0 ]			H _D # 0	F 2
									H _D # 1	G8
									H _D # 2	F 8
									H _D # 3	E 6
									H _D # 4	G2
									H _D # 5	H 6
									H _D # 6	H 2
									H _D # 7	F 6
									H _D # 8	D 4
									H _D # 9	H 3
									H _D # 1 0	M9
									H _D # 1 1	M 11
									H _D # 1 2	J1
									H _D # 1 3	J2
									H _D # 1 4	N 12
									H _D # 1 5	J6
									H _D # 1 6	P 2
									H _D # 1 7	L2
									H _D # 1 8	R 2
									H _D # 1 9	N 9
									H _D # 2 0	L6
									H _D # 2 1	M5
									H _D # 2 2	J3
									H _D # 2 3	N 2
									H _D # 2 4	R 1
									H _D # 2 5	N 5
									H _D # 2 6	N 6
									H _D # 2 7	P 13
									H _D # 2 8	N 8
	Layout Notice:								H _D # 2 9	L7
									H _D # 3 0	N 10
									H _D # 3 1	M3
	10 mils wide, 20 mils spacing								H _D # 3 2	Y 3
									H _D # 3 3	A D 14
									H _D # 3 4	Y 6
									H _D # 3 5	Y 10
		M C H _ H R C O MP							H _D # 3 6	Y 12
									H _D # 3 7	Y 14
		R 10 4							H _D # 3 8	Y 7
									H _D # 3 9	W 2
		2 4. 9_ 1 % _ 04							H _D # 4 0	A A 8
									H _D # 4 1	Y 9
									H _D # 4 2	A A 13
									H _D # 4 3	A A 9
									H _D # 4 4	A A 11
									H _D # 4 5	A D 11
									H _D # 4 6	A D 10
									H _D # 4 7	A D 13
	Layout Notice:								H _D # 4 8	A E 12
									H _D # 4 9	A E 9
									H _D # 5 0	A A 2
	MCH_HSWING a 10 mils traces								H _D # 5 1	A D 8
									H _D # 5 2	A A 3
	and 20 mils spacing
									H _D # 5 3	A D 3
									H _D # 5 4	A D 7
									H _D # 5 5	A E 14
		1 . 0 5 V S							H _D # 5 6	A F 3
									H _D # 5 7	A C 1
									H _D # 5 8	A E 3
									H _D # 5 9	A C 3
									H _D # 6 0	A E 11
				R 9 6					H _D # 6 1	A E 8
									H _D # 6 2	A G2
			2 21 _ 1 % _0 4						H _D # 6 3	A D 6
				10mils				M C H _H S W I N G		C 5
								M C H _H R C OM P		E 3
1 . 0 5V S				R 9 5	C 1 36
		1 00 _ 1 % _0 4			0 . 1 u _ 10 V _ 0 4					C 12
					2	H _ C P U R S T #
	R 9 1									E 11
					2	H _ C P U S L P #
	1 K _ 1 % _0 4
				10mils			100mil Z 0 4 0 1			A 11
										B 11
	R 9 0				C 1 28
	2 K _ 1 % _0 4				* 0 . 1u _ 1 0 V _0 4

U 2 5 A

H _ D # _ 0

H _ D # _ 1

H _ D # _ 2

H _ D # _ 3

H _ D # _ 4

H _ D # _ 5

H _ D # _ 6

H _ D # _ 7

H _ D # _ 8

H _ D # _ 9

H _ D # _ 1 0

H _ D # _ 1 1

H _ D # _ 1 2

H _ D # _ 1 3

H _ D # _ 1 4

H _ D # _ 1 5

H _ D # _ 1 6

H _ D # _ 1 7

H _ D # _ 1 8

H _ D # _ 1 9

H _ D # _ 2 0

H _ D # _ 2 1

H _ D # _ 2 2

H _ D # _ 2 3

H _ D # _ 2 4

H _ D # _ 2 5

H _ D # _ 2 6

H _ D # _ 2 7

H _ D # _ 2 8

H _ D # _ 2 9

H _ D # _ 3 0

H _ D # _ 3 1

H _ D # _ 3 2

H _ D # _ 3 3

H _ D # _ 3 4

H _ D # _ 3 5

H _ D # _ 3 6

H _ D # _ 3 7

H _ D # _ 3 8

H _ D # _ 3 9

H _ D # _ 4 0

H _ D # _ 4 1

H _ D # _ 4 2

H _ D # _ 4 3

H _ D # _ 4 4

H _ D # _ 4 5

H _ D # _ 4 6

H _ D # _ 4 7

H _ D # _ 4 8

H _ D # _ 4 9

H _ D # _ 5 0

H _ D # _ 5 1

H _ D # _ 5 2

H _ D # _ 5 3

H _ D # _ 5 4

H _ D # _ 5 5

H _ D # _ 5 6

H _ D # _ 5 7

H _ D # _ 5 8

H _ D # _ 5 9

H _ D # _ 6 0

H _ D # _ 6 1

H _ D # _ 6 2

H _ D # _ 6 3

H _ S W I N G H _ R C OM P

H _ C P U R S T# H _ C P U S L P #

H _ A V R E F H _ D V R E F

C A N T I GA

HOST

H_ A #_ 3 H _ A #_ 4

H _ A #_ 5 H _ A #_ 6

H _ A #_ 7 H _ A #_ 8 H _ A #_ 9

H_ A # _1 0

H_ A # _1 1

H_ A # _1 2 H _ A # _1 3

H_ A # _1 4 H _ A # _1 5

H_ A # _1 6 H _ A # _1 7

H_ A # _1 8

H_ A # _1 9 H _ A # _2 0

H_ A # _2 1 H _ A # _2 2

H_ A # _2 3 H _ A # _2 4

H_ A # _2 5

H_ A # _2 6 H _ A # _2 7

H_ A # _2 8 H _ A # _2 9

H_ A # _3 0 H _ A # _3 1

H_ A # _3 2

H _ A # _3 3 H _ A # _3 4 H _ A # _3 5

H_A D S # H _ A D S T B #_ 0

H _ A D S T B #_ 1 H _ B N R #

H_B P R I # H _ B R E Q#

H _ D E F E R #

H _ D B S Y #

H P L L _ C L K H P L L _ C L K #

H _ D P W R # H _ D R D Y #

H _ H I T #

H_H I T M#

H _L O C K # H _ T R D Y #

H_D I N V #_ 0

H _D I N V #_ 1 H _D I N V #_ 2 H _D I N V #_ 3

H_ D S T B N #_ 0

H _ D S T B N #_ 1 H _ D S T B N #_ 2 H _ D S T B N #_ 3

H _ D S TB P #_ 0

H _ D S TB P #_ 1 H _ D S TB P #_ 2

H _ D S TB P #_ 3

H_ R E Q #_ 0 H _ R E Q #_ 1

H_ R E Q #_ 2

H _ R E Q #_ 3 H _ R E Q #_ 4

H _ R S #_ 0

H _ R S #_ 1

H _ R S #_ 2

A 1 4		H _ A # 3	H _A #[ 3 5 : 3 ] 2
C 1 5		H _ A # 4
F	1 6	H _ A # 5
H 1 3		H _ A # 6
C 1 8		H _ A # 7
M 1 6		H _ A # 8
J	1 3	H _ A # 9
P	1 6	H _ A # 1 0
R 1 6		H _ A # 1 1
N 1 7		H _ A # 1 2
M 1 3		H _ A # 1 3
E	1 7	H _ A # 1 4
P	1 7	H _ A # 1 5
F	1 7	H _ A # 1 6
G 2 0		H _ A # 1 7
B	1 9	H _ A # 1 8
J	1 6	H _ A # 1 9
E	2 0	H _ A # 2 0
H 1 6		H _ A # 2 1
J	2 0	H _ A # 2 2
L	1 7	H _ A # 2 3
A	1 7	H _ A # 2 4
B	1 7	H _ A # 2 5
L	1 6	H _ A # 2 6
C 2 1		H _ A # 2 7
J	1 7	H _ A # 2 8
H 2 0		H _ A # 2 9
B	1 8	H _ A # 3 0
K	1 7	H _ A # 3 1
B	2 0	H _ A # 3 2
F	2 1	H _ A # 3 3
K	2 1	H _ A # 3 4
L	2 0	H _ A # 3 5
H 1 2			H _A D S #	2
B	1 6
			H _A D S T B # 0		2
G 1 7
A 9			H _A D S T B # 1 2
			H _B N R #	2
F	1 1
			H _B P R I #	2
G 1 2
			H _B R 0 #	2
E	9		H _D E F E R #		2
B 1 0
			H _D B S Y # 2
A H 7
			C L K _ MC H _ B C LK 18
A H 6
J 1 1			C LK _M C H _ B C L K # 1 8
			H _D P W R #	2
F	9
			H _D R D Y #	2
H 9
			H _H I T #	2
E	1 2		H _H I T M#	2
H 1 1
			H _L O C K # 2
C 9
			H _T R D Y #	2
J	8		H _D I N V #0	2
L	3
			H _D I N V #1	2
Y 1 3
			H _D I N V #2	2
Y 1
			H _D I N V #3	2
L	1 0
			H _D S T B N #0		2
M 7
			H _D S T B N #1 2
A A 5
			H _D S T B N #2		2
A E 6
			H _D S T B N #3 2
L	9		H _D S T B P # 0 2
M 8
A A 6			H _D S T B P # 1		2
			H _D S T B P # 2		2
A E 5
			H _D S T B P # 3 2
B	1 5	H _ R E Q# 0	H _R E Q #[ 4 : 0 ] 2
K	1 3	H _ R E Q# 1
F	1 3	H _ R E Q# 2
B	1 3	H _ R E Q# 3
B	1 4	H _ R E Q# 4
B	6		H _R S # 0	2
F	1 2
			H _R S # 1	2
C 8
			H _R S # 2	2

Pin Name	Strap Description	Configuration
		000 = 1066
CFG2: 0	FSB Freguency	010 = 800
		011 = 667
		Ot hers = Reserved
CFG4: 3	Res erved
CFG5	DMI x2 Select	Low = DMI x2
		High = DMI x4 (Default)
CFG6	Integrated Trusted	Low = The ITPM Host Interface is enabled
	Platform Module(ITPM)	High = Disabled (Def ault)
	Hos t Interf ace
	Intel Management	Low = Intel Management Engine Crypto Transport Lay er
CFG7		Security (TLS) c pheri	suite w ith no c onfidentiality
	Engine Crypt o
		High = Intel Management Engine Cry pto TLS cipher suite
	Strap
		w ith conf dentiality (def ault)
CFG8	Res erved
CFG9	PCIe Graphics Lane	Low = Reverse Lanes, 15 ->0, 14->1 etc
		High = Normal operation (default ):
		Lane Numbered ni Order
CFG10	PCIe Loopback	Low = Enabled
	enable	High = Disabled (default)
CFG11	Res erved
CFG12	ALLZ	Low = ALLZ mode enabled
		High = Disabled (default)
CFG13	XOR	Low = XOR mode enabled
		High = Disabled (default)
CFG15:14	Res erved
CFG16	FSB Dy namic ODT	Low = Dynamic ODT disabled
		High = Dynamic ODT enabled (default)
CFG18:17	Res erved
		Low = Normal operation (Default):
		Lane Numbered ni Order
CFG19	DMI Lane Reversal	High = Reverse Lanes
		DMIx 4 mode [(G)MCH->ICH]:
		(3->0, 2-> 1, 1->2 and 0- >3)
		DMIx 2 mode [(G)MCH->ICH]:
		(3->0, 2->1)
	Digital Display Port	Low = Only digital display port (SDVO/DP/iHDMI)
		or PCIe si operat onali (def ault)
	(SDVO/ DP/iHDMI)	High = Digital display port (SDVO/DP/iHDMI)
CFG20	Concurrent w thi	and PCIe are operating s multaneouslyi
	PCIe	v ai t he PEG port

Sheet 4 of 42

Cantiga 1/6, Host

B.Schematic Diagrams

D VT: Del C127

2 , 3 , 5 , 9 , 1 3, 16 , 1 8 , 3 3 1. 0 5 V S

Cantiga 1/6, Host B - 5