Clevo M860TU Cantiga 2/6, PEG

Schematic Diagrams

B - 6 Cantiga 2/6, PEG

B.Schematic Diagrams

Cantiga 2/6, PEG

Sheet 5 of 42

Cantiga 2/6, PEG

DMI_ TXP 3 1 4

H_ DPRS T P#2,13,35

M_ V R E F _M C H

M_ CLK_ DDR 2 1 1

GM_ DAC _ B28

PEG_TXN8

R109 *10mil_short

3.3VS

PEG_TXP6

C 1 55 0. 1 u_ 1 0V _ 04

R112 0_04

GTP5

PM_ NC20

C 1 65 0. 1 u_ 1 0V _ 04

CL_DATA0 15

M_ C K E 1 1 0

PM _EXTT S0#

MCH_ CF G_ 1 0

R7 2

*1 K _0 4

ALLZ

DDPC _CT _ DATA

PEG_TXN4

R81 0_04

MC H _ CF G_ 5

R12 8

4 9 . 9_ 1% _0 4

3. 3 V S

R119 0_04

DF GT_ VID_3 30

PM_ NC9

PEG_ RXN7

R129

* 2. 2 1K _ 1 % _ 04 CL K_ DREF _ SS# 1 8

GTP0

GM_ LV D S _L 1P

Z0505

Z0 5 69

C 1 52 0. 1 u_ 1 0V _ 04

SDVO_ CT_DATA

R1 6 3

1K_1% _04

C 1 48 0. 1 u_ 1 0V _ 04

R82 *2.37K_1% _04

PCIe Graphics Lane

DMI Ln e Rever sal

1.05VS

CL _R ST # 0 1 5

PEG_ RXP5

PM_ RSTIN#

Z0575

M_V R EF _ MCH

MCH_ CF G_ 1 6

P E G _ R X N [ 0. . 1 5]

C 1 56 0. 1 u_ 1 0V _ 04

R7 8

*1 K _0 4

Q5 1

*2 N3 90 4

E C

M_ C S 1# 1 0

Z0507

PM _EXTT S1#

Low= XOR mode enabled

High = Dis a bl e (Default)

PM_ NC1

GTP3

GM_ LV D S _L 2P

1.5V

PEG_TXP3

Z0562

Z0509

MCH_ CF G_ 1 6

MC H _ CF G_ 6

C 1 68 0. 1 u_ 1 0V _ 04

R122

* 2. 2 1K _ 1 % _ 04

C 1 45 0. 1 u_ 1 0V _ 04

R1 47

1K_1%_04

DELAY _P W RGD15 , 35

M_ CLK_ DDR 0# 10

MC H _ CF G_ 9

R359 0_04

DMI_ TXP 2 1 4

MC H _ TS A T N#

PEG_TXN5

C 1 53 0. 1 u_ 1 0V _ 04

Z0511

Z0572

Z05 82

Z0518

M_ CLK_ DDR 3# 11

PEG_ RXP11

Z0517

C 1 69 0. 1 u_ 1 0V _ 04

DMI_ RXP1 1 4

DMI_ TXP 0 1 4

R114 0_04

GM_ LVDS_UCLKN12

DMI_ TXN0 14

MC H _ C L K R E Q # 18

GM_ LV D S _U 0 P

L_C TRL_CLK

1. 0 5V M

MC H_ CF G_ 13

MC H _ CF G_ 4

GM_DAC_HSYNC28

PEG_ RXP3

C 1 46 0. 1 u_ 1 0V _ 04

R94 0_04

Low= disable

High=enable(Default) GTN11

PEG _CO MP

MC H _C F G _9

G M_ LVDS_U0P12

M_ CLK_ DDR 1 1 0

Z0535

C253

2. 2 u _6 . 3V _ 06

DMI_ TXP 1 1 4

GM_LVD S_LCLKN

Z0574

DDPC _CT _ CLK

PM_ NC12

GTP9

SM _RC OMP

GM _E DID _DA T A

DF GT_ VR_E N 3 0

PEG_ RXN5

PEG_TXP12

C255

2 . 2u _6 . 3V _ 0 6

C 1 41 0. 1 u_ 1 0V _ 04

R101 0_04

CL K_ DREF # 18

GTP11

PM_ NC14

PM_ NC4

PM_ NC19

PM_ NC8

R7 9

*4.02K_1%_04

C 1 44 0. 1 u_ 1 0V _ 04

Low=Interface is enable

H igh= disable(Default)

PM_ NC16

GTN8

Z05 83

C 1 62 0. 1 u_ 1 0V _ 04

C 1 43 0. 1 u_ 1 0V _ 04

FSB D ynamic ODT

G M_ LVDS_L1N12

GTP15

MC H _C F G _1 9

C 1 64 0. 1 u_ 1 0V _ 04

GTN3

SM_RCOM P_VOH

PEG_TXN14

PEG_ RXP12

G M_ LVDS_U1N12

PEG_ RXP2

MCH _CLKREQ#

MP W R OK 1 5

1. 5 V _P W R G D 15 , 3 1

Z0514

MCH_ CF G_ 1 0

R146

511_1% _04

C254

2.2u_6.3V_06

GM_DAC_VSYNC28

ME _ J_ TM S

SM_ RCOM P#

R85 0_04

M_ CLK_ DDR 1# 10

Z0576

GTP2

Z0510

GTP13

Z05 85

PM_ EXT TS1#

GTN1

ITP M Hos t Inter face

CL_CLK0 15

GTP12

SDVO_ CT_DATA

R113 0_04

R366

* 2. 2 1K _ 1 % _ 04

MC H _C F G _1 2

CL _VRE F

R7 7

10K_1% _04

SM _RC OMP_VO L

MCH_ CF G_ 1 4

SM_ RCO MP_VOH

PEG_TXP9

R3 63 *2 .21 K _ 1% _0 6

1.5V

3. 3 V S2,3,9,12,13,14,15,16,1 9 ,20 ,21 ,22 ,2 3,2 4,2 5 ,2 6 , 28 , 30 , 32 , 3 3, 3 5, 3 6 ,37,38

G M_ LVDS_U2P12

Z0 5 67

Z0 5 71

GM_ LV D S _L 1N

PM _S Y N C #15

PEG_TXN7

PEG_TXP1

SM_R COMP#

C 1 67 0. 1 u_ 1 0V _ 04

clo ck u n-ga ting

Low= Reverse Lanes

H i gh = N or m a l

Operation(Default)

Low=Only(D efault)

H ig h= s im ul t a ne ou s ly

1. 5 V7,9,10,11,27,31,33

MC H_BSEL218

M_ C S 2# 1 1

M_ OD T 0 1 0

C2 1 0

0 . 1u _1 0 V _0 4

M_ CLK_ DDR 2# 11 GM _E DID_ DA T A12

PM_ NC25

C 1 47 0. 1 u_ 1 0V _ 04

G M_ LVDS_L2N12

GM_ LV D S _U 2 P

PM_ NC3

PEG_ RXN1

PEG_ RXN1 1

3. 3 V S

MCH_TSATN#

C 1 66 0. 1 u_ 1 0V _ 04

C 1 54 0. 1 u_ 1 0V _ 04

ME _ J_ TC K

L ow = N or m al o pe r at i o n( D e f a ul t )

High=Reverse Lanes

M_ C K E 2 1 1

Z0502

PEG_ RXN0

PEG_ RXP14

C2 51

0.01u_50V_04

R160

80 . 6_ 1 %_ 04

R1 6 2

3. 0 1K _ 1% _ 04

PM _E X TT S 0#10

GTN 15

MC H _ CF G_ 8

R75 *30.1_1%_04

Digital Dispaly Po rt Concu rr ent wiht PC i e

DMI_ TXN1 14

M_ CLK_ DDR 0 1 0

DF GT_ VID_1 30

PEG_ RXN4

GM_BLON12

DMI_ RXP0 1 4

GTN 5

PEG_TXP4

M_ C K E 0 1 0

MCH_ CF G_ 1 7

PEG_TXP2

SDVO_ CT_CL K

R103 0_04

PM_ NC17

PEG_TXN1

DMI_ RXN 2 1 4

CL K_ DRE F 1 8

PEG_ RXN9

RT 1

N TC_100K_06

PM_ DPRSLPVR15 , 3 5

PM_ NC18

PEG_ RXP7

PEG_ RXN8

GM _E DID _CL K

C 1 74 0. 1 u_ 1 0V _ 04

C 1 49 0. 1 u_ 1 0V _ 04

3.3VS

Z0504

G M_ LVDS_U1P12

G M_ LVDS_U2N12

PEG_TXN6

PM_ NC2

PEG_TXN15

MC H _ CF G_ 7

R161

80 . 6_ 1 %_ 04

C 1 75 0. 1 u_ 1 0V _ 04

PEG_TXP13

MCH_ CF G_ 1 5

MC H _C F G _2 0

G M_ LVDS_L2P12

MCH_ CF G_ 1 8

PE G_R XN[0 ..1 5]37

PEG_ TXN[0..15]

Low= ALLZ mode enabled

High = Dis a bl e (Default)

GM _E N A V DD12

G M_ LVDS_L0N12

SDVO_ CT_CL K

GTP8

DF GT_ VID_4 30

M_ OD T 3 1 1

PEG_TXN[0..15 ]37

GTN 9

Z0515

PEG_TXN13

PEG_TXP15

GTN 2

PEG_ RXP[0..15]

DVT: For PM

PM_ TH RMT RIP#2,13

PM_ NC22

PEG_ RXN6

GTP7

PEG_ RXN2

R1 2 6 *1 0m i l_ s ho rt

R1 6 4

1K_1% _04

GTN 0

GTP1

PEG_ RXP1

PEG_ RXN1 0

PEG_ RXN1 3

R127 0_04

R80 *30.1_1%_04

GM_ LVDS_LC LKP12

PEG_ RXP8

MCH_ CF G_ 1 9 C 1 60 0. 1 u_ 1 0V _ 04

C2 52

0.01u_50V_04

GM_ DDC_ DA TA28

GM_ LVDS_UCLKP12

ME _ J_ TD I

PEG_TXP0

MC H _C F G _5

R105 0_04

DMI X2 se lect

GM_ DAC _ G28

M_ C S 0# 1 0

DMI_ RXP2 1 4

M_ OD T 1 1 0

PEG_TXP7

GTN 12

PM_ NC10

PEG_TXN9

R156

1 0 K _1 % _ 04

DVT: F o r PM

GM_LVD S_LCLKP

R74 0_04

VCC_ PEG

C 1 51 0. 1 u_ 1 0V _ 04

M_ CLK_ DDR 3 1 1

PEG_TXP8

PM_ NC6

R115 *10K_04

MCH_ CF G_ 2 0

L_C TRL_CLK

GTP14

PEG_ RXN1 5

GM_ LV D S _U 1 P

R364

*2.21K_1%_04

R108 *10mil_short

CL K_ PCIE_ 3GPL L # 1 8

PEG_ RXP6

PM_ NC23

GTN 10

GM_ LV D S _UC LK P

Z0573

C 1 61 0. 1 u_ 1 0V _ 04

R157

1 0 K _1 % _ 04

Z0501

Z0561

Z0506

MC H _ CF G_ 7 DMI_ RXN 3 1 4

CL K_ DREF _ SS 18

GM _E DID_ CL K12

DMI_ TXN3 14

PEG_ RXP0

1. 0 5V S2 , 3, 4 , 9, 1 3, 1 6 ,18,33

GM_ LV D S _U 0 N

PEG_ RXP15

R3 68 5 6_ 04

Q2 1

*2 N3 90 4

E C

DF GT_ VID_0 30

Z0508

MCH_ CF G_ 1 3

M_ C S 3# 1 1

DMI_ RXN 1 1 4

SM_RCOM P_VOL

PEG_TXP[0..15]37

MC H _ CF G_ 6

PEG_ RXN3

GTN 4

L_C TRL_DATA

LVDS

PCI-EXPRE SS GRAPHICS

TV VGA

U2 5C

CANT IGA

T37

T36

H4 4

J46

L44

L40

N4 1

P48

N4 4

T43

U4 3

Y43

Y48

Y36

AA4 3

AD37

AC47

AD39

H4 3

J44

L43

L41

N4 0

P47

N4 3

T42

U4 2

Y42

W47

Y37

AA4 2

AD36

AC48

AD40

J41

Y40

M4 0

M4 2

R4 8

N3 8

T40

U3 7

U4 0

M4 6

AA4 6

AA3 7

AA4 0

AD43

AC46

M4 7

J42

L46

M4 8

M3 9

M4 3

R4 7

N3 7

T39

U3 6

U3 9

Y39

Y46

AA3 6

AA3 9

AD42

AD46

M32

M33

K33

J33

M29

C44

B43

E37

E38

C41

C40

H47

E46

G40

D45

F40

B37

A37

A41

H38

G37

G38

F37

G32

F25

H25

K25

H24

E28

H32

J32

G28

J29

E29

J28

G29

L29

H48

B42

L32

C31

E32

A40

B40

J37

K37

PEG_ COMPI

PEG_C OMPO

PEG_ RX#_0

PEG_ RX#_1

PEG_ RX#_2

PEG_ RX#_3

PEG_ RX#_4

PEG_ RX#_5

PEG_ RX#_6

PEG_ RX#_7

PEG_ RX#_8

PEG_ RX#_9

PEG _RX#_10

PEG _RX#_11

PEG _RX#_12

PEG _RX#_13

PEG _RX#_14

PEG _RX#_15

PEG _R X_0

PEG _R X_1

PEG _R X_2

PEG _R X_3

PEG _R X_4

PEG _R X_5

PEG _R X_6

PEG _R X_7

PEG _R X_8

PEG _R X_9

PEG_ RX_10

PEG_ RX_11

PEG_ RX_12

PEG_ RX_13

PEG_ RX_14

PEG_ RX_15

PEG_TX#_0

PEG_TX#_10

PEG_TX#_3

PEG_TX#_4

PEG_TX#_5

PEG_TX#_6

PEG_TX#_7

PEG_TX#_8

PEG_TX#_9

PEG_TX#_1

PEG_TX#_11

PEG_TX#_12

PEG_TX#_13

PEG_TX#_14

PEG_TX#_15

PEG_TX#_2

PEG_ TX_0

PEG_ TX_1

PEG_ TX_2

PEG_ TX_3

PEG_ TX_4

PEG_ TX_5

PEG_ TX_6

PEG_ TX_7

PEG_ TX_8

PEG_ TX_9

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

L_ CT RL_ CL K

L_ CT RL_ DA TA

L_ DDC _CL K

L_ DD C _DA T A

L_ VDD_ EN

LV D S _ I B G

LV D S _ V B G

LV DS_ V REF H

LV DS_ V REF L

LV DSA_ CL K #

LV DSA_ CL K

LV DSA_ DA TA# _ 0

LV DSA_ DA TA# _ 1

LV DSA_ DA TA# _ 2

LV DSA_ DA TA_ 1

LV DSA_ DA TA_ 2

LV DSB_ CL K #

LV DSB_ CL K

LV DSB_ DA TA# _ 0

LV DSB_ DA TA# _ 1

LV DSB_ DA TA# _ 2

LV DSB_ DA TA_ 1

LV DSB_ DA TA_ 2

L_ B K LT _E N

TVA_DAC

TVB_DAC

TVC_ DA C

TV _ R T N

CRT _BL UE

CRT _D DC_ CLK

CRT _D DC_ DA TA

CRT _G REEN

CRT _H SY NC

CRT_TVO_IREF

CRT _R ED

CRT_IRTN

CRT_VSYN C

LV DSA_ DA TA_ 0

LV DSB_ DA TA_ 0

L_ B K LT _C TR L

TV_DCON SEL_0

TV_DCON SEL_1

LV DSA_ DA TA# _ 3

LV DSA_ DA TA_ 3

LV DSB_ DA TA# _ 3

LV DSB_ DA TA_ 3

R20 7 * 10 mil _s ho rt

For PM

SM_ RCOM P

G M_ LVDS_U0N12

GM_ LV D S _L 0N

R 121 10K_04

PM _E X TT S 1#11

L_C TRL_DATA

GM_ LV D S _L 0P

Z0534

MC H _ CF G_ 3

PEG_TXN0

PEG_ RXP13

PEG_TXP14

G M_ LVDS_L1P12

DMI_ RXN 0 1 4

CL K_ PCIE_ 3GPL L 1 8

ME _ J_ TD O

GTP6

PEG_ RXP10

PLT_R ST#14,22,37,38

PM_ NC7

Z0513

C 1 73 0. 1 u_ 1 0V _ 04

PM

MISC

NC

DDR CLK/ CON TROL/COMPENSA TIONCLK

DMI

CFG

RSVD

GRAPHICS VIDMEHDA

ME JTAG

U25B

CANTIGA

AP2 4

AT21

AV2 4

AR24

AR21

AU24

BC28

AY2 8

AY3 6

BB3 6

BA1 7

AY1 6

AV1 6

AR13

BC36

BD17

AY1 7

BF1 5

AY1 3

BG2 2

BH21

P2 9

R2 8

P2 5

T25

R2 5

T28

P2 0

P2 4

C2 5

N2 4

M2 4

E2 1

C2 3

C2 4

N2 1

P2 1

T21

R2 0

M2 0

L21

H2 1

R2 9

N3 3

P3 2

AT 4 0

AT 1 1

B3 8

A3 8

E4 1

F41

AE4 1

AE3 7

AE4 7

AH39

AE4 0

AE3 8

AE4 8

AH40

AE3 5

AE4 3

AE4 6

AH42

AD35

AE4 4

AF4 6

AH43

AL 3 4

AN35

AK3 4

AM3 5

BG2 3

BF2 3

BH18

BF1 8

AU20

AV2 0

AY2 1

AH 9

AH10

AH12

AH13

M3 6

N3 6

R3 3

T33

B3 3

B3 2

G3 3

F33

C3 4

BF2 8

BH28

T20

R3 2

K1 2

AH37

AH36

AN36

AJ 35

AH34

BG4 8

BF4 8

BD48

BC48

BH47

BG4 7

BE4 7

BH46

BF4 6

BG4 5

BH44

BH43

BH 6

BH 5

BG 4

G3 6

E3 6

K3 6

T24

H3 6

B1 2

E4 3

F43

BH 3

E3 3

B3 1

N2 8

BF3

BH 2

BG 2

BE2

BG 1

BF1

BD 1

BC 1

AV4 2

AR36

BF1 7

B2 8

B3 0

B2 9

C2 9

A2 8

M2 8

SA_ CK_ 0

SA_ CK_ 1

SB_ CK_ 0

SA_C K#_ 0

SA_C K#_ 1

SB_C K#_ 0

SA_CKE_0

SA_CKE_1

SB_CKE_0

SB_CKE_1

SA_C S#_ 0

SA_C S#_ 1

SB_C S#_ 0

SB_C S#_ 1

SM_D RAMRST#

SA_OD T_0

SA_OD T_1

SB_OD T_0

SB_OD T_1

SM_ RCOMP

SM_ RCO MP#

CFG_18

CFG_19

CF G_ 2

CF G_ 0

CF G_ 1

CFG_20

CF G_ 3

CF G_ 4

CF G_ 5

CF G_ 6

CF G_ 7

CF G_ 8

CF G_ 9

CFG_10

CFG_11

CFG_12

CFG_13

CFG_14

CFG_15

CFG_16

CFG_17

PM_ SYNC#

PM_ EXT_TS#_0

PM_ EXT_TS#_1

PW ROK

RST IN#

DPLL_REF_CLK

D P LL _R E F_ C L K #

DPLL_REF_SSCLK

DPLL_ REF_SSCL K#

DM I_RXN_ 0

DM I_RXN_ 1

DM I_RXN_ 2

DM I_RXN_ 3

DMI_RXP_0

DMI_RXP_1

DMI_RXP_2

DMI_RXP_3

DMI_ TXN_ 0

DMI_ TXN_ 1

DMI_ TXN_ 2

DMI_ TXN_ 3

DM I_T XP_ 0

DM I_T XP_ 1

DM I_T XP_ 2

DM I_T XP_ 3

ME _ JT A G_ TC K

ME _ JT A G_ TD O

ME _ JT A G_ TD I

ME _ JT A G_ TM S

RSV D22

RSV D23

RSV D24

RSV D25

PM_ DPRSTP#

SB_ CK_ 1

SB_C K#_ 1

RSV D20

RSVD5

RSVD6

RSVD7

RSVD8

RSVD1

RSVD2

RSVD3

RSVD4

GFX_VID_0

GFX_VID_1

GFX_VID_2

GFX_VID_3

GF X _ VR _E N

SM_ RCOM P_ V OH

SM _RC OMP_VOL

THERMTRIP#

DPRSL P VR

RSVD9

CL _ CLK

CL_DATA

CL _P W ROK

CL_ R ST #

CL _VR EF

NC _1

NC _2

NC _3

NC _4

NC _5

NC _6

NC _7

NC _8

NC _9

NC _1 0

NC _1 1

NC _1 2

NC _1 3

NC _1 4

NC _1 5

SDVO_CTRL CLK

SDVO_ CTRL DATA

CL KR EQ#

RSV D14

ICH _SYN C#

TS A T N #

PEG_ CLK#

PEG_ CLK

NC _1 6

GFX_VID_4

RSV D15

DDPC_ CT RL CLK

NC _1 7

NC _1 8

NC _1 9

NC _2 0

NC _2 1

NC _2 2

NC _2 3

NC _2 4

NC _2 5

SM_VR EF

SM _PW ROK

SM_ REXT

RSV D17

HDA_ B CLK

HD A_ RST #

H DA_SDI

HD A_S DO

HDA_ SYNC

DDPC_CT RLDATA

RSV D21

M_ C K E 3 1 1

PM_ NC21

PM_ NC15

R93 *0_04

XO R

DF GT_ VID_2 30

DMI_ TXN2 14

R110

* 2. 2 1K _ 1 % _ 04

PEG_TXP10

PEG_ RXP4

GTP10

R98 *0_04

GM_DDC_CLK28

PEG_RXP[0..15]37

GTN 6

PEG_TXN2

Z0 5 70

C 1 72 0. 1 u_ 1 0V _ 04

Lo w = X 2

H i gh =X 4( D ef au lt )

Z0503

GM_ LV D S _L 2N

PEG_TXP11

Z05 81

R111 0_04

GM_ LV D S _UC LK N

PEG_ TXP[0..1 5]

PM_ NC24

R362

* 2. 2 1K _ 1 % _ 04

For PM

PEG_ RXN1 2

GTN 13

PEG_ RXN1 4

R3 67

*4.02K_1%_04

DMI_ RXP3 1 4

M_ OD T 2 1 1

MC H_ T H E R M 2 2

PEG_TXN12

GM_ LV D S _U 2 N

PEG_TXN10

C 1 70 0. 1 u_ 1 0V _ 04

R148 100_1%_04

MC H_BSEL018

MCH_ ICH _SY NC # 1 5

GTN 7

PEG_TXN11

PM_ NC11

C 1 50 0. 1 u_ 1 0V _ 04

R155 499_1%_04

G M_ LVDS_L0P12

MC H_BSEL118

GM_ LVDS_LC LKN12

PM_ EXT TS0#

GM_ LV D S _U 1 N

Z0512

PEG_TXP5

PM_ NC5

Z0516

GM_ DAC _ R28

DDR3 _ DRA MRS T# 1 0 ,11

Z0 5 68

PEG_ RXP9

C 1 42 0. 1 u_ 1 0V _ 04

R120 *10K_04

3. 3 V S

GTN 14

PM_ NC13

C 1 71 0. 1 u_ 1 0V _ 04

R3 65 *2 .21 K _ 1% _0 6

R 125 10K_04

MCH_ CF G_ 1 1

GTP4

PEG_TXN3

MCH_ CF G_ 1 2

C 1 63 0. 1 u_ 1 0V _ 04