Technical Reference Guide

8259 Mode

The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259- equivalent logic. Table 4-8 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first.

Table 4-8.Maskable Interrupt Priorities and Assignments

 

 

 

Table 4-8.

 

 

Maskable Interrupt Priorities and Assignments

 

Priority

Signal Label

Source (Typical)

 

1

IRQ0

Interval timer 1, counter 0

 

 

2

IRQ1

Keyboard

 

 

3

IRQ8-

Real-time clock

 

 

4

IRQ9

Unused

 

 

5

IRQ10

PCI devices/slots

 

 

6

IRQ11

Audio codec

 

 

7

IRQ12

Mouse

 

 

8

IRQ13

Coprocessor (math)

 

 

9

IRQ14

Primary IDE controller

 

 

10

IRQ15

Secondary IDE I/F controller

 

 

11

IRQ3

Serial port (COM2)

 

 

12

IRQ4

Serial port (COM1)

 

 

13

IRQ5

Network interface controller

 

 

14

IRQ6

Diskette drive controller

 

 

15

IRQ7

Parallel port (LPT1)

 

 

--

IRQ2

NOT AVAILABLE (Cascade from interrupt controller 2)

 

APIC Mode

The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt processing with the following advantages:

Eliminates the processor’s interrupt acknowledge cycle by using a separate (APIC) bus

Programmable interrupt priority

Additional interrupts (total of 24)

The APIC mode accommodates eight PCI interrupt signals (INTA-..INTH-) for use by PCI devices. The PCI interrupts are evenly distributed to minimize latency and wired as follows:

ICH2

 

PCI

PCI

 

PCI

 

 

 

AGP

NIC

USB

 

 

 

 

 

Int. Cntlr.

 

Slot 1

Slot 2

 

Slot 3

 

Slot 4

Slot 5

Slot

I/F [1]

I/F #2

INTA-

 

INTA-

INTD-

 

INTC-

 

INTB-

INTD-

--

--

--

INTB-

 

--

--

 

--

 

--

--

--

--

--

INTC-

Wired

INTB-

INTA-

 

INTD-

 

INTC-

INTA-

INTA-

--

--

INTD-

to

--

--

 

--

 

--

--

INTB-

--

--

INTE-

 

--

--

 

--

 

--

---

--

INTA-

--

INTF-

 

INTC-

INTB-

 

INTA-

 

INTD-

INTB-

--

--

--

INTG-

 

INTD-

INTC-

 

INTB-

 

INTA-

INTC-

--

--

--

INTH-

 

--

--

 

--

 

--

--

--

--

INTC-

NOTES:

 

 

 

 

 

 

 

 

 

 

 

[1]Connection internal to the ICH2. Will be reported by BIOS as using INTA but is NOT shared with other functions using INTA.

Desktop and configurable minitower systems only.

Configurable minitower systems only.

Compaq Evo and Workstation Personal Computers4-17

Featuring the Intel Pentium 4 Processor

Second Edition - January 2003

Page 71
Image 71
Compaq W4000 Apic Mode, Maskable Interrupt Priorities and Assignments, Priority Signal Label Source Typical, Slot