CY62137EV30 MoBL®

Features

•Very high speed: 45 ns

•Wide voltage range: 2.20V–3.60V

•Pin-compatible with CY62137CV30

•Ultra-low standby power

—Typical standby current: 1∝A

—Maximum standby current: 7∝A

•Ultra-low active power

—Typical active current: 2 mA @ f = 1 MHz

•Easy memory expansion with CE, and OE features

•Automatic power-down when deselected

•CMOS for optimum speed/power

•Byte power-down feature

•Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII package

2-Mbit (128K x 16) Static RAM

Functional Description[1]

The CY62137EV30 is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features ad- vanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW).

Writing to the device is accomplished by asserting Chip En- able (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16).

Reading from the device is accomplished by asserting Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.

The CY62137EV30 is available in 48-ball VFBGA and 44-pin TSOPII packages.

Logic Block Diagram

 

 

DATA IN DRIVERS

 

 

A10

 

 

 

 

 

 

 

 

 

 

 

 

A9

 

 

 

 

 

 

 

 

A8

 

ROW DECODER

 

 

 

 

 

 

A7

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

A5

 

 

128K x 16

 

 

A4

 

 

RAM Array

SENSEAMPS

I/O

– I/O

A3

 

 

 

 

0

7

 

 

 

 

I/O8 – I/O15

A2

 

 

 

 

A1

 

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

 

 

 

 

 

COLUMN DECODER

 

 

 

CE

 

11

 

 

 

 

BHE

Power -Down

 

 

 

 

 

WE

 

BHE

A 12

13

14 15

16

 

CE

Circuit

 

 

 

 

BLE

A

A

A A A

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

198 Champion Court • San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-05443 Rev. *B

 

Revised February 14, 2006

[+] Feedback

Page 2
Page 1
Image 1
Cypress CY62137EV30 manual Features, Functional Description1, Logic Block Diagram, Cypress Semiconductor Corporation
Page 2

CY62137EV30 specifications

Cypress Semiconductor, a well-established name in the semiconductor industry, offers a range of memory solutions, one of which is the CY62137EV30. This product is a high-performance CMOS SRAM (Static Random Access Memory) that has gained recognition for its versatility and reliability. The CY62137EV30 is designed for various applications requiring fast access times and low power consumption.

One of the main features of the CY62137EV30 is its high-speed operation, with access times as fast as 30 ns. This capability allows the device to provide quick read and write cycles, making it suitable for applications that demand rapid data processing. The memory device operates with a voltage supply of 3.0V to 3.6V, ensuring compatibility with low-voltage digital circuits.

The device boasts a large memory capacity of 512 Kbit, organized in a 64K x 8 configuration. This structure allows for efficient data storage and retrieval, catering to applications such as telecommunications, consumer electronics, and automotive systems, where reliable data handling is crucial. The integrated memory cell design further enhances its performance, providing better speed and efficiency compared to traditional memory solutions.

Another significant characteristic of the CY62137EV30 is its low power consumption. It features a low standby current, making it ideal for battery-operated devices where power efficiency is essential. This characteristic aligns with current industry trends focusing on energy-efficient designs, contributing to longer battery life and reduced operational costs.

The CY62137EV30 also incorporates advanced technologies, such as an easy-to-use asynchronous interface. This feature simplifies the integration of the SRAM into various systems, as it allows for straightforward communication without the need for complex control signals. Additionally, the device is designed to withstand extended temperature ranges, further enhancing its reliability in diverse environmental conditions.

In summary, the Cypress CY62137EV30 stands out due to its high-speed performance, significant storage capacity, low power consumption, and ease of integration. These features make it a preferred choice for a wide range of applications, ensuring that it meets the demands of modern electronic devices and systems. As the need for efficient memory solutions continues to grow, the CY62137EV30 positions itself as a key player in the SRAM market.
Top Page Image Contents