Cypress manual Switching Characteristics Over the Operating Range, CY62137EV30 MoBL

CY62137EV30

MoBL®

Switching Characteristics Over the Operating Range [11]

					45 ns
Parameter			Description				Unit
				Min.		Max.
Read Cycle
tRC	Read Cycle Time			45			ns
tAA	Address to Data Valid					45	ns
tOHA	Data Hold from Address Change			10			ns
tACE		LOW to Data Valid				45	ns
	CE
tDOE		LOW to Data Valid				22	ns
	OE
tLZOE		LOW to LOW Z[12]		5			ns
	OE
tHZOE		HIGH to High Z[12, 13]				18	ns
	OE
t		LOW to Low Z[12]		10			ns
	CE
LZCE
t		HIGH to High Z[12, 13]				18	ns
	CE
HZCE
tPU		LOW to Power-Up		0			ns
	CE
tPD		HIGH to Power-Down				45	ns
	CE
tDBE						45	ns
	BLE/BHE LOW to Data Valid
tLZBE				5			ns
	BLE/BHE LOW to Low Z[12]
tHZBE						18	ns
	BLE/BHE HIGH to HIGH Z[12, 13]
Write Cycle[14]
tWC	Write Cycle Time			45			ns
tSCE		LOW to Write End		35			ns
	CE
tAW	Address Set-Up to Write End			35			ns
tHA	Address Hold from Write End			0			ns
tSA	Address Set-Up to Write Start			0			ns
tPWE		Pulse Width		35			ns
	WE
tBW				35			ns
	BLE/BHE LOW to Write End
tSD	Data Set-Up to Write End			25			ns
tHD	Data Hold from Write End			0			ns
t		LOW to High-Z[12, 13]				18	ns
	WE
HZWE
tLZWE		HIGH to Low-Z[12]		10			ns
	WE

Notes:

10.BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

11.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.

12.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

13.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high- impedance state.

14.The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.

Document #: 38-05443 Rev. *B Page 5 of 12

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