CY62148E MoBL®
Document #: 38-05442 Rev. *F Page 5 of 10
Switching Characteristics (Over the Operating Range) [12]
Parameter Description 45 ns 55 ns [2]
Unit
Min Max Min Max
Read Cycle
tRC Read Cycle Time 45 55 ns
tAA Address to Data Valid 45 55 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 45 55 ns
tDOE OE LOW to Data Valid 22 25 ns
tLZOE OE LOW to LOW Z [13] 55ns
tHZOE OE HIGH to High Z [13, 14] 18 20 ns
tLZCE CE LOW to Low Z [13] 10 10 ns
tHZCE CE HIGH to High Z [13, 14] 18 20 ns
tPU CE LOW to Power up 00ns
tPD CE HIGH to Power down 45 55 ns
Write Cycle [15]
tWC Write Cycle Time 45 55 ns
tSCE CE LOW to Write End 35 40 ns
tAW Address Setup to Write End 35 40 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup to Write Start 0 0 ns
tPWE WE Pulse Width 35 40 ns
tSD Data Setup to Write End 25 25 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High-Z [13, 14] 18 20 ns
tLZWE WE HIGH to Low-Z [13] 10 10 ns
Notes
12.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels
of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page4.
13.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
14.tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15.The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
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