Cypress CY62157E manual Features, Functional Description1, Logic Block Diagram

CY62157E MoBL®

8-Mbit (512K x 16) Static RAM

Features

•Very high speed: 45 ns

•Wide voltage range: 4.5V–5.5V

•Ultra-low standby power —Typical Standby current: 2 ∝A —Maximum Standby current: 8 ∝A (Industrial)

•Ultra-low active power

— Typical active current: 1.8 mA @ f = 1 MHz

•Ultra-low standby power

•Easy memory expansion with CE1, CE2 and OE features

•Automatic power-down when deselected

•CMOS for optimum speed/power

•Available in Pb-free 44-pin TSOP II and 48-ball VFBGA package

Functional Description[1]

The CY62157E is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are

0through IO15) are placed in

a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW).HIGH). The input/output pins (IO

Writing to the device is accomplished by taking Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18).

Reading from the device is accomplished by taking Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See the truth table at the back of this data sheet for a complete description of read and write modes.

Logic Block Diagram

A10
A9
A8	DECODER
A45
A7
A6
A	ROW
A2
A3
A1
A0

DATA IN DRIVERS

512K x 16 RAM Array

SENSE AMPS

IO0–IO7

IO8–IO15

	COLUMN DECODER
								BHE	CE2
								WE
11	12	13	14	15	16	17	18
									CE1
								OE
A A A			A	A	A A		A

BLE

POWER-DOWN		CE2
CIRCUIT	BHE

BLE CE 1

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05695 Rev. *C		Revised November 21, 2006

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