Cypress CY62157E Switching Characteristics Over the Operating Range, Min Max Unit Read Cycle

CY62157E MoBL®

Switching Characteristics Over the Operating Range [12]

45 ns

55 ns

Parameter

Description

Min

Max

Min

Max

Unit

Read Cycle

tRC

Read Cycle Time

45

55

ns

tAA

Address to Data Valid

45

55

ns

tOHA

Data Hold from Address Change

10

10

ns

tACE

1 LOW and CE2 HIGH to Data Valid

45

55

ns

CE

tDOE

LOW to Data Valid

22

25

ns

OE

tLZOE

LOW to LOW Z[13]

5

5

ns

OE

tHZOE

HIGH to High Z[13, 14]

18

20

ns

OE

t

LOW and CE

HIGH to Low Z[13]

10

10

ns

CE

1

LZCE

2

t

HIGH and CE

LOW to High Z[13, 14]

18

20

ns

CE

1

HZCE

2

tPU

1 LOW and CE2 HIGH to Power-Up

0

0

ns

CE

tPD

1 HIGH and CE2 LOW to Power-Down

45

55

ns

CE

tDBE

45

55

ns

BLE/BHE LOW to Data Valid

tLZBE

10

10

ns

BLE/BHE LOW to Low Z[13]

tHZBE

18

20

ns

BLE/BHE HIGH to HIGH Z[13, 14]

Write Cycle[15]

tWC

Write Cycle Time

45

55

ns

tSCE

1 LOW and CE2 HIGH to Write End

35

40

ns

CE

tAW

Address Set-Up to Write End

35

40

ns

tHA

Address Hold from Write End

0

0

ns

tSA

Address Set-Up to Write Start

0

0

ns

tPWE

Pulse Width

35

40

ns

WE

tBW

35

40

ns

BLE/BHE LOW to Write End

tSD

Data Set-Up to Write End

25

25

ns

tHD

Data Hold from Write End

0

0

ns

tHZWE

LOW to High-Z[13, 14]

18

20

ns

WE

tLZWE

HIGH to Low-Z[13]

10

10

ns

WE

Notes:

12.Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.

13.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

14.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.

15.The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the Write.

Document #: 38-05695 Rev. *C Page 5 of 12

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