Switching Waveforms

CY62158EV30 MoBL→

Read Cycle No. 1 (Address Transition Controlled)[15, 16]

ADDRESS

tOHA

tRC

tAA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Notes

15.Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

16.WE is HIGH for read cycle.

17.Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.

Document #: 38-05578 Rev. *D

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Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description Champion Court San Jose , CA Document # 38-05578 Rev. *D Ball Vfbga Pin ConfigurationsProduct Portfolio Pin Tsopii Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance9 AC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance9 Data Retention Waveform Parameter Description 45 ns Unit Min Read CycleWrite Cycle Switching Waveforms Read Cycle No Address Transition Controlled15Read Cycle No OE Controlled16 Write Cycle No WE Controlled14, 18 Write Cycle No CE1 or CE2 Controlled14, 18 Ordering Information Inputs/Outputs Mode PowerTruth Table Write Cycle No WE Controlled, OE LOW19 Package Diagrams Ball Vfbga 6 x 8 x 1 mm Pin Tsop II Issue Date Orig. Description of Change Document History