Cypress CY62158EV30 CY62158EV30 MoBL

CY62158EV30 MoBL®

Document #: 38-05578 Rev. *D Page 6 of 11

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled)[15, 16]

Read Cycle No. 2 (OE Controlled)[16, 17]

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

HIGH

ICC

ISB

IMPEDANCE

CE1

ADDRESS

CE2

DATA OUT

SUPPLY

CURRENT

VCC

Notes

15.Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

16.WE is HIGH for read cycle.

17.Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.

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Contents

Main 8-Mbit (1024K x 8) Static RAM CY62158EV30 MoBL Features Functional Description Logic Block Diagram CY62158EV30 MoBL Pin Configurations Product Product Portfolio VCC Range (V) Speed (ns) CY62158EV30 MoBL Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform CY62158EV30 MoBL Switching Characteristics CY62158EV30 MoBL Switching Waveforms Read Cycle No. 2 (OE Controlled)[16, 17] Read Cycle No. 1 (Address Transition Controlled)[15, 16] Document #: 38-05578 Rev. *D Page 7 of 11 Write Cycle No. 1 (WE Controlled)[14, 18, 19] Write Cycle No. 2 (CE1 or CE2 Controlled)[14, 18, 19] CY62158EV30 MoBL Truth Table Ordering Information Switching Waveforms Package Diagrams Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150-*D Page Document History Page