CY62167DV18 MoBL→

16-Mbit (1M x 16) Static RAM

Features

•Very high speed: 55 ns

•Wide voltage range: 1.65V–1.95V

•Ultra low active power

—Typical active current: 1.5 mA @ f = 1 MHz

—Typical active current: 15 mA @ f = fmax

•Ultra low standby power

•Easy memory expansion with CE1, CE2, and OE features

•Automatic power down when deselected

•CMOS for optimum speed and power

•Available in Pb-free 48-ball VFBGA package

Functional Description[1]

The CY62167DV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL→) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99% when addresses are not toggling. Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when:

•Deselected (CE1 HIGH or CE2 LOW)

•Outputs are disabled (OE HIGH)

•Both Byte High Enable (BHE) and Byte Low Enable (BLE) are disabled (BHE, BLE HIGH)

•Write operation is active (CE1 LOW, CE2 HIGH and WE LOW)

To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A19). If BHE is LOW then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19).

To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If BHE is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes.

Logic Block Diagram

 

DATA IN DRIVERS

 

 

 

 

 

A10

 

 

 

 

 

 

 

 

 

 

A 9

ROWDECODER

 

 

 

 

 

SENSE AMPS

 

 

 

A 8

 

 

 

 

 

 

 

 

A 7

 

1M × 16

 

 

 

 

A 6

 

 

 

 

 

A 5

RAM Array

 

 

IO –IO

7

A 4

 

 

 

 

 

 

0

 

 

 

 

 

 

IO8–IO15

A 3

 

 

 

 

 

 

A 2

 

 

 

 

 

 

 

 

 

 

A 1

 

 

 

 

 

 

 

 

 

 

A 0

 

 

 

 

 

 

 

 

 

 

 

COLUMN DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

BYTE

 

 

 

 

 

 

 

 

 

 

BHE

 

 

11

12

13

14

15 16 17 18

19

 

 

WE

CE2

 

 

 

 

CE1

 

A A A A A A A A A

 

 

OE

PowerDown

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLE

 

Circuit

BHE

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

BLE

 

 

 

 

 

CE1

 

 

Note

 

 

 

 

 

 

 

 

 

 

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Cypress Semiconductor Corporation

• 198 Champion Court • San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-05326 Rev. *C

 

Revised April 25, 2007

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Cypress CY62167DV18 manual Features, Functional Description1, Logic Block Diagram, Cypress Semiconductor Corporation
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CY62167DV18 specifications

The Cypress CY62167DV18 is a high-performance, low-power static RAM (SRAM) device designed for a variety of applications where speed and efficiency are critical. This memory chip is especially notable for its compact footprint and advanced features, making it ideal for use in portable electronics, consumer products, telecommunications, and networking equipment.

One of the main features of the CY62167DV18 is its access time of 10 nanoseconds, allowing for rapid data retrieval and processing. With a data width of 16 bits, the device provides significant data bandwidth, which is essential for modern applications requiring fast processing capabilities. It operates on a power supply voltage of 1.8V, thereby ensuring low power consumption, which is a crucial factor in battery-operated devices.

The CY62167DV18 employs Cypress’s advanced SRAM technology, which improves speed while reducing latency. This SRAM is fabricated using a highly reliable process technology that enhances durability and performance. Additionally, the chip's static nature eliminates the need for refresh cycles, contributing to quick access times and more straightforward system designs compared to dynamic RAM (DRAM).

Another characteristic of the CY62167DV18 is its compatibility with various memory bus standards, including the popular 32-bit asynchronous interface. This adaptability allows the chip to easily integrate into existing designs without requiring major modifications. Furthermore, the device supports a wide temperature range, making it suitable for both consumer and industrial applications.

The CY62167DV18 comes with built-in features such as a chip enable input (CE), write enable input (WE), and output enable input (OE). These functionalities streamline control and management of memory access, enabling engineers to design efficient and reliable systems. The chip is available in a compact 48-ball BGA (Ball Grid Array) package, which saves space on printed circuit boards and enhances thermal performance.

In summary, the Cypress CY62167DV18 is a robust, high-speed SRAM solution that combines advanced technology with low power consumption. Its impressive access times, low-voltage operation, compatibility with multiple standards, and compact design make it a versatile choice for a broad range of applications, from consumer electronics to sophisticated industrial systems. As the demand for faster and more efficient memory solutions continues to grow, the CY62167DV18 stands out as a reliable option for developers seeking to enhance their product performance.
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