16-Mbit (1M x 16) Static RAM
CY62167DV18 MoBL®
CypressSemiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05326 Rev. *C Revised April 25, 2007
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–1.95V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
Functional Description[1]
The CY62167DV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE1 HIGH
or CE2 LOW or both BHE and BLE are HIGH). The input and
output pins (IO0 through IO15) are placed in a high impedance
state when:
• Deselected (CE1 HIGH or CE2 LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)
are disabled (BHE, BLE HIGH)
• Write operation is active (CE1 LOW, CE2 HIGH and WE
LOW)
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then
data from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A19). If BHE is LOW
then data from IO pins (IO8 through IO15) is written into the
location specified on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and
CE2 HIGH) and OE LOW while forcing the WE HIGH. If BLE
is LOW, then data from the memory location specified by the
address pins appear on IO0 to IO7. If BHE is LOW, then data
from memory appears on IO8 to IO15. See the “Truth Table” on
page 9 for a complete description of read and write modes.
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Logic Block Diagram
1M × 16
RAM Array IO0–IO7
ROW DECODER
A 8
A 7
A 6
A 5
A 2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A 4
A 3IO8–IO15
WE
BLE
BHE
A16
A 0
A 1
A17
A 9
A18
A10
CE2
CE1
A19
BYTE
Power Down
Circuit BHE
BLE
CE2
CE1
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