Cypress CY62167DV18 CY62167DV18 MoBL

CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 6 of 11

Switching Waveforms

Read Cycle 1 (Address Transition Controlled)[14, 15]

Read Cycle 2 (OE Controlled)[15, 16]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes

14.The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.

15.WE is HIGH for read cycle.

16.Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.

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Contents

Main 16-Mbit (1M x 16) Static RAM CY62167DV18 MoBL Features Functional Description Logic Block Diagram CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 2 of 11 Product Portfolio Product VCC Range (V) Speed (ns) Pin Configuration Maximum Ratings Operating Range DC Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 6 of 11 Switching Waveforms Read Cycle 2 (OE Controlled)[15, 16] Read Cycle 1 (Address Transition Controlled)[14, 15] CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 7 of 11 Write Cycle 1 (WE Controlled)[13, 17, 18] Write Cycle 2 (CE1 or CE2 Controlled)[13, 17, 18] Switching Waveforms CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 8 of 11 Write Cycle 3 (WE Controlled, OE LOW)[18] t Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18] Truth Table Ordering Information Document #: 38-05326 Rev. *C Page 10 of 11 Package Diagrams Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178 51-85178-** Document History Page