Cypress CY62167DV18 manual Switching Characteristics Over the Operating Range, Write Cycle

								CY62167DV18 MoBL→
Switching Characteristics (Over the Operating Range)[10]
Parameter						Description		55 ns		Unit
							Min		Max
Read Cycle
tRC	Read Cycle Time						55			ns
tAA	Address to Data Valid								55	ns
tOHA	Data Hold from Address Change						10			ns
tACE		1 LOW and CE2 HIGH to Data Valid							55	ns
	CE
tDOE			LOW to Data Valid						25	ns
	OE
t			LOW to LOW Z[11]				5			ns
	OE
LZOE
t			HIGH to High Z[11, 12]						20	ns
	OE
HZOE
t				LOW and CE		HIGH to Low Z[11]	10			ns
	CE	1			2
LZCE
tHZCE		1 HIGH and CE2 LOW to High Z[11, 12]							20	ns
	CE
tPU		1 LOW and CE2 HIGH to Power up					0			ns
	CE
tPD		1 HIGH and CE2 LOW to Power down							55	ns
	CE
tDBE	BLE/BHE LOW to Data Valid								55	ns
tLZBE							5			ns
	BLE/BHE LOW to Low Z[11]
tHZBE									20	ns
	BLE/BHE HIGH to HIGH Z[11, 12]
Write Cycle[13]
tWC	Write Cycle Time						55			ns
tSCE		1 LOW and CE2 HIGH to Write End					40			ns
	CE
tAW	Address Setup to Write End						40			ns
tHA	Address Hold from Write End						0			ns
tSA	Address Setup to Write Start						0			ns
tPWE			Pulse Width				40			ns
	WE
tBW							45			ns
	BLE/BHE LOW to Write End
tSD	Data Setup to Write End						25			ns
tHD	Data Hold from Write End						0			ns
t			LOW to High- [11, 12]						20	ns
	WE
HZWE
tLZWE			HIGH to Low-Z[11]				10			ns
	WE

Notes

10.Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.

11.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

12.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

13.The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 38-05326 Rev. *C Page 5 of 11

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