Cypress CY62167DV18 CY62167DV18 MoBL

CY62167DV18 MoBL®

Document #: 38-05326 Rev. *C Page 2 of 11

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA) Standby ISB2 (µA)

f = 1MHz f = fmax

Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max

CY62167DV18LL 1.65 1.8 1.95 55 1.5 5 15 30 2.5 20

Pin Configuration [3]

Notes

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.

3. DNU pins must be left floating or tied to VSS to ensure proper operation.

A11

A10

A3CE1

IO10

IO8

IO9

IO11

IO13

IO12

IO14

IO15

VSS

IO0

BHE

CE2

A17

BLE

IO2

IO1

IO3

IO4

IO5IO6

IO7

A15

A14

A13

A12

A19

A18 DNU

326

A16

DNU

VCC

VCC VSS

48-Ball VFBGA

Top Vi ew

[+] Feedback

Contents

Main 16-Mbit (1M x 16) Static RAM CY62167DV18 MoBL Features Functional Description Logic Block Diagram CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 2 of 11 Product Portfolio Product VCC Range (V) Speed (ns) Pin Configuration Maximum Ratings Operating Range DC Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 6 of 11 Switching Waveforms Read Cycle 2 (OE Controlled)[15, 16] Read Cycle 1 (Address Transition Controlled)[14, 15] CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 7 of 11 Write Cycle 1 (WE Controlled)[13, 17, 18] Write Cycle 2 (CE1 or CE2 Controlled)[13, 17, 18] Switching Waveforms CY62167DV18 MoBL Document #: 38-05326 Rev. *C Page 8 of 11 Write Cycle 3 (WE Controlled, OE LOW)[18] t Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18] Truth Table Ordering Information Document #: 38-05326 Rev. *C Page 10 of 11 Package Diagrams Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178 51-85178-** Document History Page