Cypress CY62256 Read Cycle No 12, Write Cycle No WE Controlled, Write Cycle No CE Controlled

			CY62256
Switching Waveforms (continued)
Read Cycle No. 2 [12, 13]		tRC
CE
	tACE
OE
	tDOE	tHZOE
		tHZCE
	tLZOE		HIGH
DATA OUT	HIGH IMPEDANCE	DATA VALID	IMPEDANCE
	tLZCE	tPD
	tPU
VCC			ICC
SUPPLY	50%		50%
CURRENT			ISB
	[9, 14, 15]

Write Cycle No. 1 (WE Controlled)

	tWC
ADDRESS
CE
	tAW	tHA
tSA	tPWE
WE
OE
	tSD	t
		HD

DATA I/O	NOTE 16		DATAIN VALID
		tHZOE

[9, 14, 15]

Write Cycle No. 2 (CE Controlled)

	tWC
ADDRESS
CE	tSCE
tSA
tAW		tHA
WE
	tSD	tHD
DATA I/O	DATAIN VALID
Notes:

13.Address valid prior to or coincident with CE transition LOW.

14.Data I/O is high impedance if OE = VIH.

15.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Document #: 38-05248 Rev. *B Page 5 of 11