Cypress CY62256 CY62256

CY62256

Document #: 38-05248 Rev. *B Page 5 of 11

Notes:

13. Address valid prior to or coincident with CE transition LOW.

14. Data I/O is high impedance if OE = VIH.

15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high -impedance st ate.

Switching Waveforms (continued)

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

DATA OUT HIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOE

tHZCE

tPD

HIGH

VCC

SUPPLY

CURRENT

Read Cycle No. 2 [12, 13]

tHD

tSD

tPWE

tSA

tHA

tAW

tWC

DATA I/O

ADDRESS

tHZOE

DATA

INVALID

NOTE

Write Cycle No. 1 (WE Controlled) [9, 14, 15]

16

tWC

tAW

tSA

tHA

tHD

tSD

tSCE

DATA I/O

ADDRESS

DATA

INVALID

Write Cycle No. 2 (CE Controlled) [9, 14, 15]

Contents

Main 256K (32K x 8) Static RAM Features Functional Description Logic Block Diagram CY62256 Document #: 38-05248 Rev. *B Page 2 of 11 Pin Configurations f = fMAX = 1/tRC Parameter Description Test Conditions Capacitance Electrical Characteristics AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics Switching Waveforms CY62256 Document #: 38-05248 Rev. *B Page 5 of 11 Switching Waveforms Write Cycle No. 2 (CE Controlled) [9, 14, 15] Read Cycle No. 2 CY62256 Document #: 38-05248 Rev. *B Page 6 of 11 Switching Waveforms Write Cycle No. 3 (WE Controlled, O E LOW) [10, 15] Document #: 38-05248 Rev. *B Page 7 of 11 Typical DC and AC Characteristics Truth Table Ordering Information Page Package Diagrams