Cypress CY62256 CY62256

CY62256

Document #: 38-05248 Rev. *B Page 6 of 11

Note:

16. During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

DATA I/O

ADDRESS

tHD

tSD

tLZWE

tSA

tHA

tAW

tWC

tHZWE

DATA

INVALID

Write Cycle No. 3 (WE Controlled, O E LOW) [10, 15]

NOTE 16

Contents

Main 256K (32K x 8) Static RAM Features Functional Description Logic Block Diagram CY62256 Document #: 38-05248 Rev. *B Page 2 of 11 Pin Configurations f = fMAX = 1/tRC Parameter Description Test Conditions Capacitance Electrical Characteristics AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics Switching Waveforms CY62256 Document #: 38-05248 Rev. *B Page 5 of 11 Switching Waveforms Write Cycle No. 2 (CE Controlled) [9, 14, 15] Read Cycle No. 2 CY62256 Document #: 38-05248 Rev. *B Page 6 of 11 Switching Waveforms Write Cycle No. 3 (WE Controlled, O E LOW) [10, 15] Document #: 38-05248 Rev. *B Page 7 of 11 Typical DC and AC Characteristics Truth Table Ordering Information Page Package Diagrams