Cypress CY62256 Switching Characteristics , Switching Waveforms

CY62256
Document #: 38-05248 Rev. *B Page 4 of 11
Switching Characteristics Over the Operating Range[6]
Parameter Description
CY62256−55 CY62256−70
UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low-Z[7] 5 5 ns
tHZOE OE HIGH to High-Z[7, 8] 20 25 ns
tLZCE CE LOW to Low-Z[7] 5 5 ns
tHZCE CE HIGH to High-Z[7, 8] 20 25 ns
tPU CE LOW to Power-up 0 0ns
tPD CE HIGH to Power-down 55 70 ns
Write Cycle[9, 10]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Address Set-up to Write End 45 60 ns
tHA Address Hold from Write End 0 0ns
tSA Address Set-up to Write Start 0 0ns
tPWE WE Pulse Width 40 50 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Hold from Write End 0 0ns
tHZWE WE LOW to High-Z[7, 8] 20 25 ns
tLZWE WE HIGH to Low-Z[7] 5 5 ns
Switching Waveforms
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device .
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC T est Loads . T rans ition is me asured ±500 mV from steady-state voltage.
9. The internal Write time of the memory is def ined by the ov erla p of C E LOW and WE LOW. Both signals must be LOW to initiate a Wr ite and either signa l can terminate
a Write by going HIGH. The data input set-up and hold timing s hould be referen ced to the r ising edge of th e si gnal that termi nates the Write.
10. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is th e sum of tHZWE and tSD
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for Read cycle.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1
[11, 12]