CY7B9910

CY7B9920

Pin Configuration

 

 

 

 

SOIC

 

 

 

 

 

 

 

Top View

 

 

REF

 

 

1

 

24

 

 

 

 

 

 

 

VCCQ

 

2

 

23

 

 

 

 

 

 

 

 

 

 

 

 

FS

 

3

 

22

 

 

 

 

 

 

 

NC

 

4

 

21

 

 

 

 

 

 

 

VCCQ

 

 

5

 

20

 

 

 

 

 

 

 

 

 

 

 

 

VCCN

 

6

7B9910

19

 

 

 

 

 

 

 

 

 

 

 

Q0

 

7

7B9920

18

 

 

 

 

 

 

 

 

 

 

 

Q1

 

8

 

17

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

9

 

16

 

 

 

 

 

 

 

Q2

 

 

10

 

15

 

 

 

 

 

 

 

Q3

 

 

11

 

14

 

 

VCCN

 

 

12

 

13

 

 

 

 

 

 

 

 

GND TEST NC GND

VCCN

Q7

Q6

GND

Q5

Q4

VCCN

FB

Pin Definitions

Signal Name

IO

Description

 

 

 

REF

I

Reference frequency input.This input supplies the frequency and timing against which all functional

 

 

variations are measured.

FB

I

PLL feedback input (typically connected to one of the eight outputs).

 

 

 

FS[1,2,3]

I

Three level frequency range select.

TEST

I

Three level select. See TEST MODE.

 

 

 

Q[0..7]

O

Clock outputs.

 

 

 

VCCN

PWR

Power supply for output drivers.

VCCQ

PWR

Power supply for internal circuitry.

GND

PWR

Ground.

 

 

 

Test Mode

The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and CY7B9920 to operate as described in Block Diagram Description. For testing purposes, any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins.

If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.

Notes

1.For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2.

2.The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appearing at the REF and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a frequency multiplication by using external division in the feedback path of value X.

3.When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V.

Document Number: 38-07135 Rev. *B

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Cypress CY7B9910, CY7B9920 manual Pin Configuration, Pin Definitions, Test Mode, Signal Name Description