Cypress CY7B9920 Capacitance, Switching Characteristics, Parameter Description Test Conditions

CY7B9910

CY7B9920

Capacitance

Tested initially and after any design or process changes that may affect these parameters.
Parameter	Description	Test Conditions	Max	Unit
CIN	Input Capacitance	TA = 25°C, f = 1 MHz, VCC = 5.0V	10	pF

AC Test Loads and Waveforms
	5V		3.0V
	R1	R1=130	2.0V
		R2=91	Vth =1.5V
		CL = 50 pF (CL = 30pF for –5 and – 2 devices)	0.8V
CL	R2	(Includes fixture and probe capacitance)	0.0V
			≤1ns
		7B9910–3

2.0V

Vth =1.5V 0.8V

≤1ns

7B9910–4

TTL AC Test Load (CY7B9910) TTL Input Test Waveform (Cy7B9910)

	VCC
		R1
CL		R2

R1=100

R2=100

CL = 50 pF (CL =30 pF for –5 and – 2devices) (Includes fixture and probe capacitance)

7B9910–5

80% Vth = VCC/2 20%

0.0V

≤ 3ns

VCC

80%

Vth = VCC/2

20%

≤ 3ns

7B9910–6

CMOS AC Test Load (CY7B9920)				CMOS Input Test Waveform (CY7B9920)
Switching Characteristics
Over the Operating Range [11]
			CY7B9910–2[8]			CY7B9920–2[8]
Parameter	Description		Min	Typ	Max	Min	Typ	Max	Unit
fNOM	Operating Clock	FS = LOW[1, 2]	15		30	15		30	MHz
	Frequency in MHz
		FS = MID[1, 2]	25		50	25		50
		FS = HIGH[1, 2, 3]	40		80	40		80[12]
tRPWH	REF Pulse Width HIGH		5.0			5.0			ns
tRPWL	REF Pulse Width LOW		5.0			5.0			ns
tSKEW	Zero Output Skew (All Outputs)[13, 14]			0.1	0.25		0.1	0.25	ns
tDEV	Device-to-Device Skew[14, 15]				0.75			0.75	ns
tPD	Propagation Delay, REF Rise to FB Rise		–0.25	0.0	+0.25	–0.25	0.0	+0.25	ns
t	Output Duty Cycle Variation[16]		–0.65	0.0	+0.65	–0.65	0.0	+0.65	ns
ODCV
t	Output Rise Time[17, 18]		0.15	1.0	1.2	0.5	2.0	2.5	ns
ORISE
t	Output Fall Time[17, 18]		0.15	1.0	1.2	0.5	2.0	2.5	ns
OFALL
tLOCK	PLL Lock Time[19]				0.5			0.5	ms
tJR	Cycle-to-Cycle Output Jitter	Peak to Peak			200			200	ps
		RMS			25			25	ps

Document Number: 38-07135 Rev. *B Page 5 of 11

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