Cypress CY7C1012DV33 AC Switching Characteristics, Read Cycle, Write Cycle 9, Parameter, Unit

					CY7C1012DV33
AC Switching Characteristics
Over the Operating Range [5]
Parameter			Description		–10		Unit
				Min		Max
Read Cycle
tpower [6]	VCC(Typical) to the First Access			100			μs
tRC	Read Cycle Time			10			ns
tAA	Address to Data Valid					10	ns
tOHA	Data Hold from Address Change			3			ns
tACE		Active LOW to Data Valid [3]				10	ns
	CE
tDOE		LOW to Data Valid				5	ns
	OE
tLZOE		LOW to Low Z [7]		1			ns
	OE
tHZOE		HIGH to High Z [7]				5	ns
	OE
tLZCE		Active LOW to Low Z [3, 7]		3			ns
	CE
tHZCE		Deselect HIGH to High Z [3, 7]				5	ns
	CE
tPU		Active LOW to Power Up [3, 8]		0			ns
	CE
tPD		Deselect HIGH to Power Down [3, 8]				10	ns
	CE
Write Cycle [9, 10]
tWC	Write Cycle Time			10			ns
tSCE		Active LOW to Write End [3]		7			ns
	CE
tAW	Address Setup to Write End			7			ns
tHA	Address Hold from Write End			0			ns
tSA	Address Setup to Write Start			0			ns
tPWE		Pulse Width		7			ns
	WE
tSD	Data Setup to Write End			5.5			ns
tHD	Data Hold from Write End			0			ns
tLZWE		HIGH to Low Z [7]		3			ns
	WE
tHZWE		LOW to High Z [7]				5	ns
	WE

Notes

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of Figure 2, unless specified otherwise.

6.tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.

7.tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured ±200 mV from steady state voltage.

8.These parameters are guaranteed by design and are not tested.

9.The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write.

10.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document Number: 38-05610 Rev. *D Page 5 of 11

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