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| CY7C1012DV33 |
Switching Waveforms (continued) |
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Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17] | ||
| tWC |
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ADDRESS |
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| tSCE |
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CE |
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tSA | tSCE | tHA |
tAW |
| |
WE | tPWE |
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| |
| tSD | tHD |
DATA I/O | DATA VALID |
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Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17] | ||
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| tWC |
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ADDRESS |
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| tSCE |
|
CE |
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| tAW |
| tHA |
| tSA | tPWE |
|
WE |
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|
OE |
| tSD |
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| t | tHD | |
| HZOE |
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DATA I/O | NOTE 18 | DATAIN VALID |
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Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]
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| tWC |
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ADDRESS |
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| tSCE |
|
CE |
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|
|
| tAW |
| tHA |
| tSA | tPWE |
|
WE |
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|
|
|
| tSD | tHD |
DATA I/O | NOTE 18 | DATA VALID |
|
| tHZWE |
| tLZWE |
Notes
16.Data I/O is high impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
18.During this period, the I/Os are in output state. Do not apply input signals.
Document Number: | Page 7 of 11 |
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