CY7C1018DV33
Data Retention Characteristics (Over the Operating Range)
Parameter | Description | Conditions | Min. | Max. | Unit | |||
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VDR | VCC for Data Retention |
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| 2 |
| V |
ICCDR | Data Retention Current | VCC = VDR = 2.0V, |
| > VCC – 0.3V, |
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| 3 | mA |
CE |
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| VIN > VCC – 0.3V or VIN < 0.3V |
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tCDR [3] | Chip Deselect to Data Retention Time |
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| 0 |
| ns |
t [12] | Operation Recovery Time |
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| t | RC |
| ns |
R |
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Data Retention Waveform
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| DATA RETENTION MODE |
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VCC | 3.0V | VDR > 2V | 3.0V |
| tCDR |
| tR |
CE |
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Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC
ADDRESS
tAA
tOHA
DATA OUT | PREVIOUS DATA VALID |
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15] |
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ADDRESS |
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CE |
| tRC |
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| tACE |
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OE |
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| tDOE | tHZOE |
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| tHZCE |
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| tLZOE | HIGH | |
DATA OUT | HIGH IMPEDANCE | DATA VALID | IMPEDANCE |
| tLZCE |
| |
| tPD |
| |
VCC | tPU | ICC | |
SUPPLY | 50% |
| 50% |
CURRENT |
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| ISB |
Notes
12.Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 ∝s or stable at VCC(min.) > 50 ∝s.
13.Device is continuously selected. OE, CE = VIL.
14.WE is HIGH for Read cycle.
15.Address valid prior to or coincident with CE transition LOW.
Document #: | Page 5 of 9 |
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