Cypress CY7C1024DV33 AC Switching Characteristics, AC Test Loads and Waveform4, Description, Unit

CY7C1024DV33

Figure 2. AC Test Loads and Waveform[4]

			50Ω
OUTPUT	Z0= 50Ω			VTH = 1.5V
		30 pF*
	(a)

3.3V	R1 317 Ω
OUTPUT	R2
5 pF*
	351Ω

*Including jig and scope

*Capacitive Load consists of all components of the test environment

3.0V

GND

Rise Time > 1V/ns

All input pulses

90%

10%

(c)

(b)

90%

10%

Fall Time:> 1V/ns

AC Switching Characteristics

Over the Operating Range [5]

Parameter

Read Cycle

Description

	–10
Min	Max

Unit

tpower[6]	VCC(Typical) to the First Access			100		μs
tRC	Read Cycle Time			10		ns
tAA	Address to Data Valid				10	ns
tOHA	Data Hold from Address Change			3		ns
tACE			Active LOW to Data Valid [3]		10	ns
	CE
tDOE			LOW to Data Valid		5	ns
	OE
tLZOE			LOW to Low Z [7]	1		ns
	OE
tHZOE			HIGH to High Z [7]		5	ns
	OE
tLZCE		Active LOW to Low Z [3, 7]		3		ns
	CE
tHZCE		Deselect HIGH to High Z [3, 7]			5	ns
	CE
tPU		Active LOW to Power Up [3, 8]		0		ns
	CE
tPD		Deselect HIGH to Power Down [3, 8]			10	ns
	CE

Notes

4.Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 μs (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of Figure 2, unless specified otherwise.

6.tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.

7.tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured ±200 mV from steady state voltage.

8.These parameters are guaranteed by design and are not tested.

Document Number: 001-08353 Rev. *C Page 4 of 9

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