Cypress CY7C1034DV33 CY7C1034DV33

CY7C1034DV33

Document Number: 001-08351 Rev. *C Page 7 of 9

Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]

Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]

Truth Table

CE1CE2CE3OE WE IO0 – IO23 Mode Power

HXXXXHigh Z Power Down Standby (I

SB)

X L X X X High Z Power Down Standby (ISB)

X X H X X High Z Power Down Standby (ISB)

L H L L H Full Data Out Read Active (ICC)

L H L X L Full Data In Write Active (ICC)

L H L H H High Z Selected, Outputs Disabled Active (ICC)

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAINVALID

NOTE 18

ADDRESS

DATA IO

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

NOTE 18

ADDRESS

DATA IO

Note

18.During this period, the IOs are in the output state and input signals are not applied.

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Contents

Main CY7C1034DV33 6-Mbit (256K X 24) Static RAM Features Functional Description Logic Block Diagram Selection Guide Pin Configuration CY7C1034DV33 Maximum Ratings Operating Range DC Electrical Characteristics Capacitance CY7C1034DV33 AC Switching Characteristics Data Retention Characteristics AC Switching Characteristics (continued) Document Number: 001-08351 Rev. *C Page 6 of 9 Switching Waveforms [+] Feedback Figure 4. Read Cycle No. 1 (Address Transition Controlled) Figure 5. Read Cycle No. 2 (OE Controlled) [3, 14, 15] Figure 6. Write Cycle No. 1 (CE Controlled) [3, 16, 17] CY7C1034DV33 Document Number: 001-08351 Rev. *C Page 7 of 9 [+] Feedback Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17] Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17] Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions