CY7C1034DV33
Document Number: 001-08351 Rev. *C Page 5 of 9
Write Cycle [9, 10]
tWC Write Cycle Time 10 ns
tSCE CE Active LOW to Write End [3] 7ns
tAW Address Setup to Write End 7 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 7 ns
tSD Data Setup to Write End 5.5 ns
tHD Data Hold from Write End 0 ns
tLZWE WE HIGH to Low Z [7] 3ns
tHZWE WE LOW to High Z [7] 5ns
Data Retention Characteristics
Over the operating range
Parameter Description Conditions [3] Min Typ Max Unit
VDR VCC for Data Retention 2 V
ICCDR Data Retention Current9 VCC = 2V, CE1, CE3 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
25 mA
tCDR [11] Chip Deselect to Data Retention Time 0 ns
tR [12] Operation Recovery Time tRC ns
Figure 3. Data Retention Waveform
AC Switching Characteristics (continued)
Over the operating range [5]
Parameter Description –10 Unit
Min Max
3.0V3.0V
tCDR
VDR> 2V
DATA RETENTION MODE
tR
CE
VCC
Notes
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW. Chip enables must be active and WE must be LOW
to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal
that terminates the write.
10.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11.Tested initially and after any design or process changes that may affect these parameters.
12.Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs.
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