CY7C1034DV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC
ADDRESS
tAA
tOHA
DATA OUT | PREVIOUS DATA VALID |
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| DATA VALID |
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| Figure 5. Read Cycle No. 2 (OE Controlled) [3, 14, 15] |
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ADDRESS |
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CE |
| tRC |
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| tACE |
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OE |
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| tDOE |
| tHZOE |
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| tHZCE |
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| tLZOE |
| HIGH | |
DATA OUT | HIGH IMPEDANCE | DATA VALID |
| IMPEDANCE |
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| tLZCE |
| tPD |
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VCC | tPU |
| ICC | |
SUPPLY | 50% |
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| 50% |
CURRENT |
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| ISB |
| Figure 6. Write Cycle No. 1 (CE Controlled) [3, 16, 17] |
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| tWC |
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ADDRESS |
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| tSCE |
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CE |
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| tSA |
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| tAW | tSCE | tHA |
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| tPWE |
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WE |
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| tSD | tHD |
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DATA IO |
| DATA VALID |
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Notes
13.Device is continuously selected. OE, CE = VIL.
14.WE is HIGH for read cycle.
15.Address valid before or similar to CE transition LOW.
16.Data IO is high impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: | Page 6 of 9 |
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