Cypress CY7C1218H

CY7C1218H

Document #: 38-05667 Rev. *B Page 13 of 16

ZZ Mode Timing[21, 22]

Notes:

21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22.DQs are in High-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

[+] Feedback

Contents

Main 1-Mbit (32K x36) Pipelined Sync SRAM CY7C1218H Features Functional Description Logic Block Diagram CY7C1218H Pin Configuration CY7C1218H Selection Guide 100-Pin TQFP Pin Definitions Functional Overview Burst Sequences Sleep Mode Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Truth Table CY7C1218H Maximum Ratings Operating Range Electrical Characteristics CY7C1218H Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing CY7C1218H Read/Write Cycle Timing Page Ordering Information Package Diagram A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Document History Page