CY7C1218H
Document #: 38-05667 Rev. *B Page 5 of 16
Interleaved Burst Address Table (MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 40 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Truth Table[2, 3, 4, 5, 6, 7]
Next Cycle Add. Used ZZ CE1CE2CE3ADSP ADSC ADV OE DQ Write
Unselected None L H X X X L X X Tri-State X
Unselected None L L X H L X X X Tri-State X
Unselected None L L L X L X X X Tri-State X
Unselected None L L X H H L X X Tri-State X
Unselected None L L L X H L X X Tri-State X
Begin Read External L L H L L X X X Tri-State X
Begin Read External L L H L H L X X Tri-State Read
Continue Read Next L X X X H H L H Tri-State Read
Continue Read Next L X X X H H L L DQ Read
Continue Read Next L H X X X H L H Tri-State Read
Continue Read Next L H X X X H L L DQ Read
Suspend Read Current L X X X H H H H Tri-State Read
Suspend Read Current L X X X H H H L DQ Read
Suspend Read Current L H X X X H H H Tri-State Read
Suspend Read Current L H X X X H H L DQ Read
Begin Write Current L X X X H H H X Tri-State Write
Begin Write Current L H X X X H H X Tri-State Write
Begin Write External L L H L H H X X Tri-State Write
Notes:
2. X = “Don't Care.” H = HIGH, L = LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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