Cypress CY7C1218H Ordering Information

CY7C1218H

Document #: 38-05667 Rev. *B Page 14 of 16

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

100 CY7C1218H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1218H-100AXI Industrial

133 CY7C1218H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1218H-133AXI Industrial

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Contents

Main 1-Mbit (32K x36) Pipelined Sync SRAM CY7C1218H Features Functional Description Logic Block Diagram CY7C1218H Pin Configuration CY7C1218H Selection Guide 100-Pin TQFP Pin Definitions Functional Overview Burst Sequences Sleep Mode Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Truth Table for Read/Write Truth Table CY7C1218H Maximum Ratings Operating Range Electrical Characteristics CY7C1218H Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing CY7C1218H Read/Write Cycle Timing Page Ordering Information Package Diagram A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Document History Page