CY7C1223H
Document #: 38-05674 Rev. *B Page 10 of 16
Switching Characteristics Over the Operating Range [14, 15]
Parameter Description
166 MHz 133 MHz
UnitMin. Max. Min. Max.
tPOWER VDD(Typical) to the first Access[10] 11 ms
Clock
tCYC Clock Cycle Time 6.0 7.5 ns
tCH Clock HIGH 2.5 3.0 ns
tCL Clock LOW 2.5 3.0 ns
Output Times
tCO Data Output Valid After CLK Rise 3.5 4.0 ns
tDOH Data Output Hold After CLK Rise 1.5 1.5 ns
tCLZ Clock to Low-Z[11, 12, 13] 00 ns
tCHZ Clock to High-Z[11, 12, 13] 3.5 4.0 ns
tOEV OE LOW to Output Valid 3.5 4.0 ns
tOELZ OE LOW to Output Low-Z[11, 12, 13] 00 ns
tOEHZ OE HIGH to Output High-Z[11, 12, 13] 3.5 4.0 ns
Set-up Times
tAS Address Set-up Before CLK Rise 1.5 1.5 ns
tADS ADSC, ADSP Set-up Before CLK Rise 1.5 1.5 ns
tADVS ADV Set-up Before CLK Rise 1.5 1.5 ns
tWES GW, BWE, BW[A:B] Set-up Before CLK Rise 1.5 1.5 ns
tDS Data Input Set-up Before CLK Rise 1.5 1.5 ns
tCES Chip Enable Set-up Before CLK Rise 1.5 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.5 0.5 ns
tADH ADSP , ADSC Hold After CLK Rise 0.5 0.5 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 ns
tWEH GW,BWE, BW[A : B] Hold After CLK Rise 0.5 0.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns
Notes:
10.This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
11.t CHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13.This parameter is sampled and not 100% tested.
14.Timing reference level is 1.5V when VDDQ = 3.3V and 1.25V when VDDQ = 2.5V.
15.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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