Read/Write Timing16, 18, Adsp Adsc | Cypress CY7C1223H specs

CY7C1223H

Read/Write Timing[16, 18, 19]

tCYC

CLK

Notes:

18.The data bus (Q) remains in High-Z following a Write cycle, unless a new read access initiated by ADSC or ADSP.

19.GW is HIGH.

A5 A6

D(A5) D(A6)

Back-to-Back

WRITEs

Document #: 38-05674 Rev. *B

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Contents

Selection Guide Features166 MHz 133 MHz Unit Cypress Semiconductor Corporation Output Logic Block Diagram CY7C1223H Pin ConfigurationsTop View Pin Descriptions Functional Overview Sleep ModeBurst Sequences Adsp Adsc ADV Write CLK A1, A0 Function ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Maximum Ratings Electrical Characteristics Over the Operating Range7Operating Range Ambient Range Capacitance9 Thermal Characteristics9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 14 Read Timing16 Switching Waveforms Undefined Write Timing16 Adsp Adsc Read/Write Timing16, 18 DON’T Care ZZ Mode Timing 20,21 Ordering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Document History Issue Date Orig. Description of Change