Cypress CY7C1223H manual Maximum Ratings, Electrical Characteristics Over the Operating Range7

CY7C1223H

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature		–65°C to +150°
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND		–0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state	–0.5V to VDDQ +0.5V

Electrical Characteristics Over the Operating Range[7, 8]

DC Input Voltage		–0.5V to VDD+0.5V
Current into Outputs (LOW)			20 mA
Static Discharge Voltage			> 2001V
(per MIL-STD-883,Method 3015)
Latch-up Current			> 200 mA
Operating Range
	Ambient
Range	Temperature (TA)	VDD	VDDQ
Com’l	0°C to +70°C	3.3V −5%/+10%	2.5V−5% to
			VDD
Ind’l	–40°C to +85°C

Parameter	Description	Test Conditions		Min.	Max.	Unit
VDD	Power Supply Voltage			3.135	3.6	V
VDDQ	I/O Supply Voltage	for 3.3V I/O		3.135	VDD	V
		for 2.5V I/O		2.375	2.625
VOH	Output HIGH Voltage	for 3.3V I/O, IOH = –4.0 mA		2.4		V
		for 2.5V I/O, IOH = –1.0 mA		2.0
VOL	Output LOW Voltage	for 3.3V I/O, IOL = 8.0 mA			0.4	V
		for 2.5V I/O, IOL = 1.0 mA			0.4
VIH	Input HIGH Voltage[7]	for 3.3V I/O		2.0	VDD + 0.3V	V
		for 2.5V I/O		1.7	VDD + 0.3V	V
VIL	Input LOW Voltage[7]	for 3.3V I/O		–0.3	0.8	V
		for 2.5V I/O		–0.3	0.7	V
IX	Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	∝A
	except ZZ and MODE
	Input Current of MODE	Input = VSS		–30		∝A
		Input = VDD			5	∝A
	Input Current of ZZ	Input = VSS		–5		∝A
		Input = VDD			30	∝A
IOZ	Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	∝A
IDD	VDD Operating Supply	VDD = Max., IOUT = 0 mA,	6-ns cycle, 166 MHz		240	mA
	Current	f = fMAX = 1/tCYC
			7.5-ns cycle,133MHz		225	mA
ISB1	Automatic CS	VDD = Max., Device Deselected,	6-ns cycle, 166 MHz		100	mA
	Power-down	VIN ≥ VIH or VIN ≤ VIL,
			7.5-ns cycle,133MHz		90	mA
	Current—TTL Inputs	f = fMAX = 1/tCYC
ISB2	Automatic CS	VDD = Max., Device Deselected,	All speeds		40	mA
	Power-down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
	Current—CMOS Inputs	f = 0
ISB3	Automatic CS	VDD = Max., Device Deselected,	6.0-ns cycle, 166 MHz		85	mA
	Power-down	or VIN ≤ 0.3V or
			7.5-ns cycle, 133MHz		75	mA
	Current—CMOS Inputs	VIN > VDDQ – 0.3V,
		f = fMAX = 1/tCYC
ISB4	Automatic CS	VDD = Max., Device Deselected,	All speeds		45	mA
	Power-down	VIN ≥ VIH or VIN ≤ VIL, f = 0
	Current—TTL Inputs

Notes:

7.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).

8.Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05674 Rev. *B Page 8 of 16

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