Cypress CY7C037AV Switching Characteristics Over the Operating Range6, Including scope and jig

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Figure 3. AC Test Loads and Waveforms

OUTPUT

C = 30 pF

3.3V

R1 = 590Ω	OUTPUT	RTH = 250Ω
R2 = 435Ω	C = 30 pF		OUTPUT
			C = 5 pF
			VTH = 1.4V

3.3V

R1 = 590Ω

R2 = 435Ω

(a) Normal Load (Load 1)	(b) Thévenin Equivalent (Load 1)	(c) Three-State Delay(Load 2)
		(Used for tLZ, tHZ, tHZWE, & tLZWE
	ALL INPUTPULSES	including scope and jig)

3.0V

GND 10%

≤3 ns

90%

90%

10%

≤ 3 ns

Switching Characteristics Over the Operating Range[6]

					CY7C027V/027VN/027AV/028V/
Parameter			Description		CY7C037V/037AV/038V							Unit
				-15			-20			-25
				Min	Max	Min		Max	Min		Max
Read Cycle
tRC	Read Cycle Time			15		20			25			ns
tAA	Address to Data Valid				15			20			25	ns
tOHA	Output Hold From Address Change			3		3			3			ns
tACE[7]	CE		LOW to Data Valid		15			20			25	ns
tDOE	OE		LOW to Data Valid		10			12			13	ns
tLZOE[8, 9, 10]	OE		LOW to Low Z	3		3			3			ns
tHZOE[8, 9, 10]	OE		HIGH to High Z		10			12			15	ns
tLZCE[8, 9, 10]	CE	LOW to Low Z		3		3			3			ns
tHZCE[8, 9, 10]	CE	HIGH to High Z			10			12			15	ns
tPU[10]	CE	LOW to Power Up		0		0			0			ns
tPD[10]	CE	HIGH to Power Down			15			20			25	ns
tABE[7]	Byte Enable Access Time				15			20			25	ns
Write Cycle
tWC	Write Cycle Time			15		20			25			ns
tSCE[7]	CE	LOW to Write End		12		16			20			ns
tAW	Address Valid to Write End			12		16			20			ns
tHA	Address Hold From Write End			0		0			0			ns
tSA[7]	Address Setup to Write Start			0		0			0			ns
tPWE	Write Pulse Width			12		17			22			ns
tSD	Data Setup to Write End			10		12			15			ns

Notes

6.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30 pF load capacitance.

7.To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.

8.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

9.Test conditions used are Load 2.

10.This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11.

Document #: 38-06078 Rev. *B Page 7 of 18

[+] Feedback