CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)[34]
CELValid First:
ADDRESS L,R
CEL
CER
BUSYR
CER ValidFirst:
ADDRESSL,R
CER
CE L
BUSYL
ADDRESS MATCH
tPS
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ADDRESS MATCH |
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tPS |
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tBLC | tBHC |
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)[34]
Left Address Valid First:
ADDRESSL
ADDRESSR
BUSY R
tRC or tWC
ADDRESS MATCH |
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tPS
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Right Address Valid First:
ADDRESSR
ADDRESSL
BUSY L
tRC or tWC
ADDRESS MATCH |
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tPS
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Note
34. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
Document #: | Page 13 of 18 |
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