CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
Figure 15. Interrupt Timing Diagrams
Left Side Sets INTR :
tWC
ADDRESSL |
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| WRITE 7FFF (FFFF for CY7C028V/38V) |
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| tHA[35] |
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| CE L |
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R/WL
INTR
| tINS [36] |
Right Side Clears INTR: | tRC |
ADDRESSR | READ 7FFF |
(FFFF for CY7C028V/38V) | |
CER |
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| tINR[36] |
R/WR |
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OE R |
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INTR |
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Right Side Sets INTL:
ADDRESSR
CE R
R/WR
INTL
tWC
WRITE 7FFE (FFFE for CY7C028V/38V)
tHA[35]
tINS[36]
Left Side Clears INT L: | tRC |
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ADDRESSR | READ 7FFE |
(FFFF for CY7C028V/38V) | |
CE L |
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| tINR[36] |
R/W L |
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OE L |
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INT L |
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Notes
35.tHA depends on which enable pin (CEL or R/WL) is deasserted first.
36.tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: | Page 14 of 18 |
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