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- page 17
Models:
CY7C027AV
CY7C027V
CY7C027VN
CY7C028V
CY7C037AV
CY7C037V
CY7C038V
1
17
18
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B
Page 17 of 18
Package Diagram
Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*C
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Contents
Main
3.3V 32K/64K x 16/18 Dual-Port Static RAM
,
Cypress Semiconductor Corporation 198 Champion Court San Jose
CA 95134-1709 408-943-2600 Document #: 38-06078 Rev. *B Revised December 09, 2008
Features
CY7C027V/027VN/027AV/028V
Pin Configurations
CY7C028V (64K x 16)
CY7C027V/027VN/027AV (32K x 16)
Figure 1. 100-Pin TQFP (Top View)
CY7C037V/037AV/038V
Pin Configurations
SB1
CY7C038V (64K x 18)
CY7C037V/037AV (32K x 18)
Architecture
Functional Description
Write Operation
Read Operation
Interrupts
Busy
Master/Slave
Semaphore Operation
Maximum Ratings
Operating Range
Capacitance
Electrical Characteristics
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V
Switching Characteristics
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V
Switching Characteristics
Data Retention Mode
Timing
Figure 4. Read Cycle No. 1 (Either Port Address Access)
Figure 6. Read Cycle No. 3 (Either Port)
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access)
Figure 7. Write Cycle No. 1: R/W Controlled Timing
Figure 8. Write Cycle No. 2: CE Controlled Timing
Figure 9. Semaphore Read After Write Timing, Either Side
Figure 10. Timing Diagram of Semaphore Contention
A
Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH)
Figure 12. Write Timing with Busy Input (M/S=LOW)
CE
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration)
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration)
RightAddres sValid First:
Valid First :
CE
Valid First:
Left Address Valid First:
Figure 15. Interrupt Timing Diagrams
Right SideClears INT
RightSide Sets INT
LeftSide Sets INT
Left SideClears INT
Page
Ordering Information
32K x16 3.3V Asynchronous Dual-Port SRAM
64K x16 3.3V Asynchronous Dual-Port SRAM
32K x18 3.3V Asynchronous Dual-Port SRAM
64K x18 3.3V Asynchronous Dual-Port SRAM
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