Package Diagram

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-*C

Document #: 38-06078 Rev. *B

Page 17 of 18

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Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Pin Tqfp Top View Pin Configurations Parameter Unit Maximum Access Time Typical Operating CurrentSelection Guide Functional Description Pin DefinitionsArchitecture Semaphore Operation BusyMaster/Slave Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Capacitance5 Including scope and jig Switching Characteristics Over the Operating Range6Read Cycle Write Cycle Timing Data Retention ModeInterrupt Timing Semaphore Timing Read Cycle No Either Port Address Access15, 16 Switching Waveforms Write Cycle No R/W Controlled Timing 20, 21, 22 CY7C027V/027VN/027AV/028V Timing Diagram of Read with Busy M/S=HIGH33 Right Address Valid First CER ValidFirst Left Side Clears INT L Right Side Clears INT RRight Side Sets Intl Operation Non-Contending Read/Write Inputs Outputs 9 -I/O 0 -I/OInterrupt Operation Example assumes Left Port Right Port Function 32K x16 3.3V Asynchronous Dual-Port Sram Ordering Information64K x16 3.3V Asynchronous Dual-Port Sram 32K x18 3.3V Asynchronous Dual-Port Sram Pin Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Package Diagram Document History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions