CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Characteristics Over the Operating Range[6](continued)
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| CY7C027V/027VN/027AV/028V/ |
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Parameter |
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| Description |
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| CY7C037V/037AV/038V |
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| Min |
| Max | Min |
| Max | Min |
| Max |
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tHD |
| Data Hold From Write End | 0 |
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| 0 |
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| 0 |
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| ns | ||||||||||||||
tHZWE[9, 10] |
| R/W | LOW to High Z |
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| 10 |
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| 12 |
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| 15 | ns | |||||||||||||
tLZWE[9 ,10] |
| R/W | HIGH to Low Z | 3 |
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| 3 |
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| 3 |
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| ns | |||||||||||||
tWDD[36] |
| Write Pulse to Data Delay |
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| 30 |
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| 40 |
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| 50 | ns | ||||||||||||||
tDDD[36] |
| Write Data Valid to Read Data Valid |
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| 25 |
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| 30 |
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| 35 | ns | ||||||||||||||
Busy Timing[11] |
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tBLA |
| BUSY | LOW from Address Match |
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| 15 |
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| 20 |
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| 20 | ns | |||||||||||||
tBHA |
| BUSY | HIGH from Address Mismatch |
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| 15 |
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| 20 |
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| 20 | ns | |||||||||||||
tBLC |
| BUSY | LOW from | CE |
| LOW |
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| 15 |
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| 20 |
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| 20 | ns | ||||||||||
tBHC |
| BUSY | HIGH from | CE | HIGH |
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| 15 |
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| 16 |
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| 17 | ns | |||||||||||
tPS |
| Port Setup for Priority | 5 |
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| 5 |
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| 5 |
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| ns | ||||||||||||||
tWB |
| R/W | HIGH after BUSY (Slave) | 0 |
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| 0 |
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| 0 |
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tWH |
| R/W | HIGH after | BUSY | HIGH (Slave) | 13 |
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| 15 |
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| 17 |
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tBDD[13] |
| BUSY | HIGH to Data Valid |
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| 15 |
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| 20 |
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| 25 | ns | |||||||||||||
Interrupt Timing[11] |
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tINS |
| INT | Set Time |
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| 15 |
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| 20 |
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| 20 | ns | |||||||||||||
tINR |
| INT | Reset Time |
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| 15 |
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| 20 |
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| 20 | ns | |||||||||||||
Semaphore Timing |
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tSOP |
| SEM Flag Update Pulse | (OE | or | SEM) |
| 10 |
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| 10 |
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| 12 |
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tSWRD |
| SEM Flag Write to Read Time | 5 |
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| 5 |
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| 5 |
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| ns | ||||||||||||||
tSPS |
| SEM Flag Contention Window | 5 |
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| 5 |
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| 5 |
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tSAA |
| SEM Address Access Time |
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| 15 |
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| 20 |
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| 25 | ns | ||||||||||||||
Data Retention Mode
The CY7C027V/027VN/027AV/028V and CY7037V/037AV/038V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention:
1.Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V.
2.CE must be kept between VCC – 0.2V and 70% of VCC during the power up and power down transitions.
Timing |
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| Data Retention Mode | ||
VCC | 3.0V | VCC > 2.0V | 3.0V |
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CE | VCC to VCC – 0.2V |
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tRC
VIH 
3.The RAM can begin operation >tRC after VCC reaches the mini- mum operating voltage (3.0 volts).
Parameter | Test Conditions[14] | Max | Unit |
ICCDR1 | At VCCDR = 2V | 50 | μA |
Notes
11.For information on
12.Test conditions used are Load 1.
13.tBDD is a calculated parameter and is the greater of
14.CE = VCC, Vin = GND to VCC, TA = 25° C. This parameter is guaranteed but not tested.
Document #: | Page 8 of 18 |
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