Cypress CY7C027AV, CY7C037AV, CY7C037V, CY7C028V, CY7C027VN, CY7C038V manual CY7C027V/027VN/027AV/028V

		CY7C027V/027VN/027AV/028V
			CY7C037V/037AV/038V
Switching Waveforms(continued)
	Figure 9. Semaphore Read After Write Timing, Either Side[29]
		tSAA	tOHA
A0–A 2	VALID ADRESS	VALID ADRESS
	tAW	tACE
	tHA
SEM
	tSCE	tSOP
	tSD
I/O 0	DATAIN VALID		DATAOUT VALID
tSA	tHD
	tPWE
R/W
	tSWRD	tDOE
OE		tSOP
	WRITE CYCLE	READ CYCLE

Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32]

A0L –A2L

R/WL

SEML

A0R–A2R

MATCH

tSPS

MATCH

R/WR

SEM R

Notes

29.CE = HIGH for the duration of the above timing (both write and read cycle).

30.I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

31.Semaphores are reset (available to both ports) at cycle start.

32.If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.

Document #: 38-06078 Rev. *B Page 11 of 18

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