Cypress CY7C1298H manual Write Timing16, Address A1 A2

CY7C1298H

Switching Waveforms (continued)

Write Timing[16, 17]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

tADS tADH

A3

tWES tWEH

BWE,

BW[A:B]

tWES tWEH

GW

tCES tCEH

CE

tADVS tADVH

ADV

ADV suspends burst

OE

Data in (D) High-Z

Data Out (Q)

tOEHZ

tt

DS DH

D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)

BURST READ Single WRITE BURST WRITE DON’T CARE

Extended BURST WRITE

UNDEFINED

Note:

17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.

Document #: 38-05665 Rev. *B Page 12 of 16

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