Cypress CY7C1298H Read/Write Timing

CY7C1298H

Document #: 38-05665 Rev. *B Page 13 of 16

Read/Write Timing[16, 18, 19]

Notes:

18.The data bus (Q) remains in High-Z following a WRITE cycle, unless a new read access initiated by ADSP or ADSP.

19.GW is HIGH.

Switching Waveforms (continued)

CYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

Data Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

BWE, BW[A:B]

DON’T CARE UNDEFINED

[+] Feedback

Contents

Main 1-Mbit (64K x 18) Pipelined DCD Sync SRAM CY7C1298H Features Functional Description Selection Guide CY7C1298H Functional Block Diagram A E ADDRESS REGISTER CY7C1298H A Pin Descriptions Functional Overview Burst Sequences Sleep Mode Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) Truth Table CY7C1298H Truth Table for Read/Write ZZ Mode Electrical Characteristics CY7C1298H Maximum Ratings Operating Range Electrical Characteristics CY7C1298H Capacitance Thermal Characteristics AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Timing [+] Feedback CY7C1298H Write Timing Read/Write Timing ZZ Mode Timing Ordering Information Package Diagram A Document History Page